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AS3524 C21 / C22 Data Sheet, Confidential
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Datasheet, Confidential
AS3524
Advanced Audio Processor System
a
1
Description
Key Features
1.1 Digital Core
Embedded 32-Bit RISC Controller
The AS3524 implements a highly flexible and fully integrated digital audio processor system combining strong calculating power and high performance interfaces commonly used within audio player systems. Using advanced 0.13m process technology and large on chip RAM leads to outstanding low power consumption of 0.3 mW/MHz for the ARM922T microcontroller core and 0.6 mW/MHz for the overall system measured with a typical MP3 player SW application. Based on a powerful ARM9TDMI capable of performing up to 200MIPS it is suited to run MP3, AAC, WMA, OGG... decoders and encoders and, in addition, it can perform extensive user interfaces, motion graphics support, video playback and much more. The AS3524 SOC (system-on-a-Chip) features dedicated high speed interfaces for ATA IDE, USB2.0 HS-OTG and SDRAM ensuring maximum performance for download, upload, and playback. Furthermore interfaces for NAND flashes, MMC/SD cards and Memory Stick ensure most flexible system design possibilities. Hardware support for parallel interfaces lower the CPU load serving complex and/or colour user interfaces. Additional serial high-speed data and control interfaces guarantee the connection to other peripherals and or processors in the system. Two independently programmable PLLs generate the required frequencies for audio playback/recording, for the processor core and for the USB interface at the same time.
* ARM922TDMI RISC CPU * 2.5Mbit on-chip RAM * 1Mbit on chip ROM * Clock speed max. 250MHz (200MIPS) * Standard JTAG interface USB 2.0 HS & OTG Interface * Up to 480Mbit/s transfer speed * USB 2.0 HS/FS physical inlcuding OTG support * USB 2.0 HS/FS digital core including OTG host * Dedicated dual port buffer RAM * DMA bus master functionality IDE Host Controller * Supporting Ultra ATA 33/66/100/133 modes * Programmable IO and Multi-word DMA capability * Dedicated dual port buffer RAM * DMA bus master functionality External Memory Controller * Dynamic memory interface * Asynchronous static memory * DMA bus master functionality DMA Controller * Single Master DMA controller * 2 DMA channels possible at the same time * 16 DMA requests supported Interrupt Controller * Support for 32 standard interrupts * Support for 16 vectored IRQ interrupts Audio Subsystem Interface * Dedicated 2 wire serial control master * I2S input and output with dual port buffer RAM Nand Flash Interface * * * 8 and 16bit flash support 3, 4 & 5 byte address support hardware ECC
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AS3524 C21 / C22 Data Sheet, Confidential MMC/SD Interface * MMC/SD Card host for multiple card support * 4 data line support for SD cards MS / MS Pro Interface * Dedicated dual port buffer RAM Display Interface * Serial and parallel controller supported * On chip hardware acceleration Synchronous Serial Interface * Master and slave operation * 8 and 16 bit support * Several protocol standards supported I2S Interface * Input multiplexed with audio subsystem * selectable SPDIF input conversion * Dedicated dual port buffer RAM 2 Wire Serial Control Interface * Master and slave operation * Standard and fast mode support General Purpose IO Interface * 4x 8-bit ports Multiple Boot Options * * * Selection of internal ROM or external boot device Internal boot loader supporting boot from external NorFlash, NandFlash, IDE, SPI host Internal USB boot loader with USB promer supporting initial factory programming and firmware update
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2
* * * *
Application
Portable Digital Audio Player and Recorder Portable Digital Media Player PDA Smartphone
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3
Figure 1
Block Diagram
AS3524 Block Diagram
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1
DESCRIPTION ........................................................................................................1
KEY FEATURES.............................................................................................................1
1.1 Digital Core....................................................................................................................................................... 1
2 3 4
4.1
APPLICATION ........................................................................................................2 BLOCK DIAGRAM..................................................................................................3 ELECTRICAL SPECIFICATIONS...........................................................................8
Absolute Maximum Ratings ............................................................................................................................ 8
4.2 Operating Conditions....................................................................................................................................... 9 4.2.1 Supply Voltages .................................................................................................................................... 9 4.2.2 Operating Currents .............................................................................................................................. 10 4.2.3 Temperature Range ............................................................................................................................. 10
5
DETAILED FUNCTIONAL DESCRIPTIONS.........................................................11
5.1 ARM922-T Processor Core ........................................................................................................................... 11 5.1.1 General ................................................................................................................................................ 11 5.1.2 Block Diagrams................................................................................................................................... 12 5.1.3 ARM922T Details ............................................................................................................................... 13 5.1.4 ARM V4T Architecture ...................................................................................................................... 13 5.1.5 JTAG Interface.................................................................................................................................... 15 5.1.6 Boot Concept....................................................................................................................................... 16 5.2 AHB Peripheral Blocks.................................................................................................................................. 18 5.2.1 2.5 MBIT RAM Main Memory........................................................................................................... 18 5.2.2 On-Chip ROM..................................................................................................................................... 19 5.2.3 VIC - Vectored Interrupt Controller ................................................................................................... 19 5.2.4 SMDMAC - Single master DMAC ..................................................................................................... 22 5.2.5 Multi Port Memory Controller (MPMC)............................................................................................. 24 5.2.6 IDE Interface....................................................................................................................................... 25 5.2.7 USB 2.0 HS OTG interface................................................................................................................. 28 5.2.8 Memory Stick / Memory Stick Pro Interface ...................................................................................... 33 5.3 APB Peripheral Block .................................................................................................................................... 35 5.3.1 Timers ................................................................................................................................................. 35 5.3.2 Watchdog Unit .................................................................................................................................... 39 5.3.3 SSP - Synchronous Serial Port ........................................................................................................... 42 5.3.4 GPIO - General purpose input/output ports......................................................................................... 44 5.3.5 MCI - SD / MMC Card Interface ....................................................................................................... 46 5.3.6 I2cAudMas - I2C audio master interface ............................................................................................ 47 5.3.7 I2CMSI - I2C master/slave interface................................................................................................... 48 5.3.8 I2SIN - I2S input interface .................................................................................................................. 49 5.3.9 SPDIF interface................................................................................................................................... 55 5.3.10 I2SOUT - I2S output interface ............................................................................................................ 56 5.3.11 NAND Flash Interface ........................................................................................................................ 62
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5.3.12 5.3.13 5.3.14 5.3.15
DBOP - Data Block Output Port ......................................................................................................... 73 UART - Universal Asynchronous Receiver/Transmitter.................................................................... 83 CGU - Clock generation unit .............................................................................................................. 90 CCU - Chip Control Unit .................................................................................................................. 104
6
6.1
PINOUT AND PACKAGING ...............................................................................109
Package Variants.......................................................................................................................................... 109
6.2 CTBGA180 Package Drawings ................................................................................................................... 109 6.2.1 Marking............................................................................................................................................. 109 6.2.2 CTBGA180 Package Ball-out ........................................................................................................... 110 6.2.3 CTBGA180 Ball List ........................................................................................................................ 110 6.3 Pad Cell Description..................................................................................................................................... 118 6.3.1 Digital Pads ....................................................................................................................................... 118
7
7.1
APPENDIX ..........................................................................................................119
Memory MAP ............................................................................................................................................... 119
7.2 Register definitions....................................................................................................................................... 121 7.2.1 Base Address definitions................................................................................................................... 121
8 9 10 11
ORDERING INFORMATION ...............................................................................122 COPYRIGHT .......................................................................................................123 DISCLAIMER ......................................................................................................123 CONTACT INFORMATION.................................................................................123
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Document Revisions
Revision 0.1 0.2 0.3 1.0 1.1 1.11 all 5.1.6.2, 8 5.3.13.1 5.1.6.2 Chapter all Date 9.3.2005 31.3.2005 14.9.2005 8.5.2006 25.9.2006 9.11.2006 Owner MMA first preliminary version MMA PKM WSG WSG WSG Description
package drawing and pinout added marking description and top view added first release of document generated added description for modified C22 bootloader added description for UART Baud rate settings corrected table headers for boot device selection and USB boot frequency settings
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Related Documents
ARM922T Technical Reference Manual ARM9TDMI Technical Reference Manual PrimeCellTM MultiPort Memory Controller; PL172 Technical Reference Manual AMBA Specification (Rev 2.0) PrimeCellTM Synchronous Serial Port; PL022 Technical Reference Manual PrimeCellTM General Purpose Input/Output; PL061 Technical Reference Manual PrimeCellTM Single Master DMA Controller; PL081 Technical Reference Manual PrimeCellTM Multimedia Card Interface; PL180 Technical Reference Manual PrimeCellTM Vectored Interrupt Controller; PL190 Technical Reference Manual CWda03 - SPDIF-AES/EBU TO I2S CONVERTER TSMC TPZ013G3 Standard I/O Library Databook DesignWare USB 2.0 HI-SPEED ON-THE-GO Controller Subsystem DesignWare USB 2 PHY Hardmacro SMS2IP mem stick host controller ICON mem stick host con interface IDE host controller BK3710S AS352x USB MSC Boot Promer specification document AS352X_USB_MSC_Boot_P romer_V07.doc IHI0011A_AMBA_SPEC.pdf DDI0184B_922T_TRM.pdf DDI0180A_9tdmi_trm.pdf http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.arm.com http://www.coreworks.pt http://www.tsmc.com http://www.synopsys.com http://www.synopsys.com http://www.sony.com http://www.sony.com http://www.palmchip.com
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4
4.1
Electrical Specifications
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under "Operating Conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The device should be operated under recommended operating conditions. Table 1 Absolute Maximum Ratings Parameter Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 5V pins Voltage difference at VSS terminals Input Current (latchup immunity) Electrostatic Discharge HBM Electrostatic Discharge HBM for USB Pins Total Power Dissipation (all supplies and outputs) Storage Temperature Lead Temperature Humidity non-condensing 5 -0.5 -0.5 -100 Max 3.7 3.7 3.7 3.7 1.68 1.68 1.68 7.0 0.5 100 +/-1 +/-2 1000 -55 125 240 85 Unit V V V V V V V V V mA kV kV mW C C % Norm: IPC/JEDEC J-SDT-020C Note digital periphery supply voltage digital IO supply for MPMC PADs USB analog supply transmit block to be connected to UVDD USB analog supply common block to be connected to UVDD digital core supply voltage core supply for critical blocks (1-TRAM) core supply forPLLA, PLLB Applicable for pins VBUS Applicable for pins vss_core, vss_peri, vss_mem, usb_vssa33t, usb_vssa33c Norm: JEDEC 17 Norm: MIL 883 E method 3015 Norm: MIL 883 E method 3015 (Pins: usb_dp, usb_dm, usb_vbus) for CTBGA180 package
Symbol VDDperi VDDmem USBVDDA33T USBVDDA33C VDDcore VDDcoreana VDDAPLL VIN_5V VIN_VSS Iscr ESD ESD_USB Pt Tstrg Tlead H
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4.2
Operating Conditions
4.2.1 Supply Voltages
Following supply voltages for the digital system are generated by internal LDOs. Table 2 Operating conditions for internal generated supply voltages Parameter Min 3.0 1.75 1.08 1.08 1.08 3.15 3.15 Difference of Negative Supplies vss_peri, vss_core, vss_core_ana, vss_mem, vssa_pll, usb_vssa33c, usb_vssa33t, Note(s) -0.1 Max 3.6 3.4 1.25 1.25 1.25 3.45 3.45 0.1 Unit V V V V V V V V Note digital periphery supply voltage digital IO supply for MPMC PADs digital core supply voltage see Note (1) core supply for critical blocks (1-TRAM) core supply forPLLA, PLLB USB analog supply transmit block to be connected to UVDD USB analog supply common block to be connected to UVDD To achieve good performance, the negative supply terminals should be connected to low impedance ground plane.
Symbol VDDperi VDDmem VDDcore VDDcoreana VDDAPLL USBVDDA33T USBVDDA33C
(1) For the VDD_CORE supply, voltage scaling should be applied to optimize power consumption and CPU speed performance. For normal operation with fclk (CPU ARM-922T clock) frequencies below 200 MHz, CVDD (supply of VDD_CORE) can be set to a lower value of 1.10 V. Only for setting fclk of the CPU to clock frequencies above 200 MHz, the VDD_CORE supply voltage must be set to 1.20 V typical conditions.
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4.2.2 Operating Currents
Table 3 Supply currents Parameter Peripheral current External memory interface current Digital core current Typ 2 20 Max 20 20 145 30 30 Unit mA mA mA mA mA (2) (1), (2) Note
Symbol IDD_PERI_OP IDD_MEM_OP IDD_CORE_OP
IDD_USBA33T_OP USB transmitter current IDD_USBA33C_OP USB common blocks current
Notes
(1) Typical condition for playback of MP3 music with 44.1 KHz / 128 kbit with 32 headphones. No external SDRAM connected. USB2.0 in standby. (2) Maximum condition for ARM running at 250 MHz, AHB/APB bus and memory at 64 MHz, USB 2.0 in HS operation.
In the case of standby mode or in the case of configuring the device to stopped clock, following current consumption is measured. Table 4 Leakage currents Parameter Typ Max 4 800 3 1.5 Unit mA A mA mA @ Tambient=25 @ Tambient=25
O O
Symbol IDD_PERI_LEAK IDD_MEM_LEAK IDD_CORE_LEAK IDD_LEAK(VDDAPLL+C OREANA)
Note Including USBA33T, USBA33C
C C
4.2.3 Temperature Range
Table 5 Temperature Range Parameter Operating temperature range Junction temperature range Thermal Resistance Min 0 0 29 Typ 25 Max 85 110 Unit C C C/W Note
Symbol Top Tj Rth
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5 5.1
Detailed Functional Descriptions
ARM922-T Processor Core
5.1.1 General
The ARM922T macrocell is a high-performance 32-bit RISC integer processor combining an ARM9TDMITM processor core with: * * * * 8KB instruction cache and 8 KB data cache Instruction and data Memory Management Unit (MMU) Write buffer with 16 data words and 4 addresses Advanced Microprocessor Bus Architecture (AMBATM) AHB interface
The ARM922T provides a high-performance processor solution for open systems requiring full virtual memory management and sophisticated memory protection. The ARM922T processor core is capable of running at 250 MHz. The ARM922T hard macrocell has a very low power consumption. The integrated cache helps to significantly reduce memory bandwith demands, improving performance and minimizing power consumption. At 250 MHz the ARM922T comsumes as little as 65 mW, making it ideal for high-performance battery operated audio or video applications. The ARM core and associated bus structures are configured for little endian byte order (compatible with Windows CETM and SymbianTM OS). Table 6 ARM 922T characteristics MMU yes AHB yes Thumb yes mW/MHz 0.25 @ 1.2 V MHz 250
Cache (I/D) 8KB / 8KB
Features
* * * * * * * * * 32-bit RISC architecture (ARMv4T) Harvard architecture with separated instruction (I) and data (D) caches with 8 KB each and 8-word line length Five stage pipeline (fetch, decode, execute, memory, write back) enabling high master clock speeds 32-bit ARM instruction set for maximum performance and flexibility 16-bit Thumb instruction set for increased code density Enhanced ARM architecture V4 MMU to provide translation and access permission checks for instruction and data addresses. With this MMU different operating systems (Windows CE, Symbian ...) can be implemented. Industry standard AMBA bus interface (AHB and APB) Hard-macro implementation The processor core clock frequency (FCLK) is programmable up to 250MHz and the ARM922 power consumption is directly proportional to this clock frequency FCLK
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5.1.2 Block Diagrams
Figure 2 ARM 922T Functional Block Diagram
Figure 3 ARM9TDMI Functional Block Diagram
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5.1.3 ARM922T Details
The ARM922T macrocell is based on the ARM9TDMI Harvard architecture processor core with an efficient five-stage pipeline. To reduce the effect of memory bandwidth and latency on performance, the ARM922T macrocell includes separate cachs and MMUs for both instructions and data. It also has a write buffer and physical address TAG RAM.
Control Coprocessor (CP15)
The control coprocessor is provided for configuration of the caches, the write buffer, and other ARM922T options. Eleven registers are available for program control: * * * * * * * Register 1 controls system operation parameters including endianness, cache, and MMU enable Register 2 and 3 configure and control MMU functions Register 5 and 6 provide MMU status information Register 7 and 9 are used for cache maintenance operations Register 8 and 10 are used for MMU maintenance operations Register 13 is used for fast context switching Register 15 is used for test.
Caches
Two 8KB caches are implemented, one for instructions, the other for data, both with an 8-word line size. Separate buses connect each cache to the ARM9TDMI core permitting a 32 bit instruction to be fetched and fed into the Decode stage of the pipeline at the same time as a 32 bit data access for the memory stage of the pipeline. Cache lock-down is provided to permit critical code sequences to be locked into the cache to ensure predictability for real-time code. The cache replacement algorithm can be selected by the operating system as either pseudo-random or round-robin. Both caches are 64-way set-associative. Lock-down operates on a per-way basis.
Debug Features
The ARM9TDMI processor core incorporates an EmbeddedICE unit and EmbeddedICE-RT logic permitting both software tasks and external debug hardware to * Set hardware and software breakpoints * Perform single-stepping * Enable access to registers and memory This functionality is implemented as a coprocessor and is accessible from hardware through the JTAG port. Full-speed, real-time execution of the processor is maintained until a breakpoint is hit. At this point control is passed either to a software handler or to JTAG control.
Write Buffer
The ARM922T macrocell also incorporates a 16-data, 4address write buffer to avoid stalling the processor when writes to external memory are performed.
PA TAG RAM
The ARM922T macrocell implements a physical address TAG RAM (PA TAG RAM) to perform write-backs from the data cache. The physical addresses of all the lines held in the data cache are stored by the PA TAG memory, removing the requirement for address translation when evicting a line from the cache.
5.1.4 ARM V4T Architecture
The ARM9TDMI processor core implements the ARMv4T Instruction Set Architecture (ISA). The ARMv4T ISA is a superset of the ARMv4 ISA with additional support for the Thumb 16-bit compressed instruction set.
MMU
The ARM922T macrocell implements an enhanced ARMv4 MMU to provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI core. The MMU features are: * * * * * * * * * Standard ARMv4 MMU mapping sizes, domains, and access protection scheme Mapping sizes are 1 MB sections, 64 KB large pages, 4 KB small pages, and new 1KB tiny pages Access permissions for sections Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpages) Access permissions for tiny pages 16 domains implemented in hardware 64-entry instruction Translation-Lookaside-Buffer (TLB) and 64-entry data TLB Hardware page table walks Round-robin replacement algorithm (also called cyclic)
Performance and Code Density
The ARM9TDMI core executes two instruction sets * 32-bit ARM instruction set * 16-bit Thumb instruction set The ARM instruction set is designed so that a program can achieve maximum performance with the minimum number of instructions. Most ARM9TDMI instructions are executed in a single cycle. The simpler Thumb instruction set offers much increased code density deducing code size and memory requirement. Code can switch between the ARM and Thumb instruction sets on any procedure call.
ARM9TDMI Integer Pipeline Stages
The integer pipeline consists of five stages to maximize instruction throughput in the ARM9TDMI core: * * * * * Fetch Decode and register read Execute shift and ALU operation, or address calculate, or multiply Memory access and multiply Write register
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AS3524 C21 / C22 Data Sheet, Confidential By using a five-stage pipeline, the ARM922T delivers a throughput approaching one instruction per cycle.
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Classes of Instructions
The ARM and Thumb instruction sets can be divided into four broad classes of instruction: * * * * Data processing instructions Load and store instructions Branch instructions Coprocessor instructions
Registers
The ARM9TDMI processor core consists of a 32-bit datapath and associated conrol logic. This datapath contains 31 generalpurpose registers, coupled to a full shifter, Arithmetic Logic Unit, and a multiplier. At any one time 16 registers are visible to the user. The remainder are mode-specific replacement registers (banked registers) used to speed up execution processing, and make nested exceptions possible. Register 15 is the Program Counter (PC) that can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer.
Data Processing Instructions
The data processing instructions operate on data held in generalpurpose registers. Of the two source operands, one is always a register. The other has two basic forms: * An immediate value * A register value optionally shifted If the operand is a shifted register, the shift can be an immediate value or the value of another register. Four types of shift can be specified. Most data processing instructions can perform a shift followed by a logical or arithmetic operation. There are two classes of multiply instructions: * Normal, 32 bit result * Long, 64 bi resut variants. Both types of multiply instruction can optionally perform an accumulate operation
Exeption Types/Modes
The ARM9TDMI core supports five types of exception, and a privileged processing mode for each type. The types of exceptions are: * * * Fast interrupt (FIQ) Normal interrupt (IRQ) Memory aborts (used to implement memory protection or virtual memory) * Attempted execution of an undefined instruction * Software interrupts (SWIs) All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used both to return after the exception is processed and to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without the need to save or restore these registers. A seventh processing mode, System mode, uses the User mode registers. System mode runs tasks that require a privileged processor mode and enables them to invoke all classes of exceptions.
Load and Store Instructions
There are two main types of laod and store instructions: * Load or store the value of a single register * Load or store multiple register values Load and store single register instructions can transfer a 32-bit word, a 16-bit halfword, or an 8-bit byte between memory and a register. Byte and halfword loads can be automatically zero extended or sign extended as they are loaded. These instructions have three primary addressing modes: * Offset * Pre-indexed * Post-indexed The address is formed by adding an immediate, or register-based, positive, or negative offset to a base register. Register-based offsets can also be scaled with shift operations. Pre-indexed and post-indexed addressing modes update the base registers with the base plus offset calculation. As the PC is a general-purpose register, a 32-bit balue can be loaded directly into the PC to perform a jump to any address in the 4GB memory space. Load and store multiple instructions perform a block transfer of any number of the general purpose registers to, or from, memory. Four addressing modes are provided: * Pre-increment addressing * Post-increment addressing * Pre-decrement addressing * Post-decrement addressing The base address is specified by a register value (that can be optionally updated after the transfer). As the subroutine return address and the PC values are in general-purpose registers, very efficient subroutine calls can be constructed.
Status Registers
All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: * * Four ALU flags (Negative, Zero, Carry, Overflow) An interrupt disable bit for each of the IRQ and FIQ interrupts * A bit to indicate ARM or Thumb execution state * Five bits to encode the current processor mode All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately before the exception occurred.
Conditional Execution
All ARM instructions can be executed conditionally and can optionally update the four condition code flags (Negative, Zero, Carry, and Overflow) according to their result. Fifteen conditions are implemented.
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Branch Instructions
As well as letting data processing or load instructions change control flow (by writing the PC) a standard branch instruction is provided with 24-bit signed offset, providing for forward and backward branches of up to 32 MB. A branch with link (BL) instruction enables efficient subroutine calls. BL preserves the address of the instruction after the branch in R14 (Link register or LR). This lets a move instruction put the LR in to the PC and return to the instruction after the branch.
The branch and exchange (BX) instruction switches between ARM and Thumb instruction sets with the return address optionally preserving the operating mode of the calling subroutine.
Coprocessor Instructions
There are three types of coprocessor instructions: * * * Coprocessor data processing instructions Coprocessor register transfer instructions Coprocessor data transfer instructions
5.1.5 JTAG Interface
The ARM933T debug interface is based on IEEE Std. 1149.1- 1990, standard test access port. The ARM922T contains hardware extensions for advanced debugging features. These are intended to ease the development of application software. The debug extensions allow the core to be stopped by one of the following: * * * A given instruction fetch (breakpoint) A data access (watchpoint) Asynchronously by a debug request
When this happens, the ARM922T is said to be in debug state. At this point, you can examine the internal state of the core and the external state of the system. When examination is complete, you can restore the core and system state and resume program execution. Normally, all control for debugging is done by running a debugger software (ARM AXD or ARM Realview Debugger) on a debug host PC. Connection to the chip is done by an ARM Multi-ICE interface, which connects either to the parallel port or the USB port of the debug host PC. The connection to the multi-ICE interface is done via a 20 way connector and ribbon cable. Following diagram shows the signals connections to the ICE connector. Figure 4 Interface connector to multi-ICE
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5.1.6 Boot Concept
It can be selected if the system should boot either using the internal ROM (internal boot loader) or an external ROM/Flash (connected to the MPMC interface). XPC[0] is read within global chip reset to do the selection of either internal or external boot. Table 7 XPC[0] 1 0 Boot definitions for internal/external boot selection Booting Option Internal ROM External ROM/Flash
For the internal bootloader, two chip versions are available: C21 and C22. Version C22 has additional features and is fully backward compatible to C21.
5.1.6.1
Internal Bootloader Version C21
Within the internal ROM boot loader several options for booting can be selected: * SSP IF - SPI master for ST serial flash types * SSP IF - SPI slave * NandFlash * Debug UART diagnostics All boot loader options of the internal bootloader are configured by XPC[3:1] pins. External pull-up or pull-down resistors should be used to configure the boot options. Table 8 0 1 2 3 4 5 6 7 Boot definitions Chip version C21 Boot Device SPI master ST M25Pxx serial Nor Flash reserved SPI slave NandFlash (SB/BB - autodetect) NandFlash (SB/BB - autodetect) UART / Command Line Interface without diagnostics UART / Command Line Interface without diagnostics UART / Command Line Interface with diagnostics 000 001 010 011 100 101 110 111
XPC[3:1]
5.1.6.2
* *
Internal Bootloader Version C22
For chip version C22 the boot loader is extended with two additional features IDE boot: direct boot from harddisk USB boot promer. In the case that a USB connection is present and either an update button is pressed or there is no bootable device, the USB promer is started (see Figure 5 Boot decision between normal boot and USB boot promer" for details). The USB boot promer allows update of the firmware by using an USB mass storage class device. This update can be used either for initial programming (factory programming) or as mechanism for an in-field firmware update.
The C22 boot loader is fully compatible to the C21 boot loader except for mode 4, where the previous NAF boot mode is replaced by IDE boot. For version C22, NAF boot is only available in mode 3. Refer to Table 9 Boot definitions Chip version C22" for details. The update button is located between xpa[4] and xpa[0]. Within the key scan routine, xpa[4] is driven shortly to each logic level "0" and "1" and the value of xpa[0] is read back to sense a keypress of the update button. For the USB promer, it is necessary that frequency settings defining the quarz crystal frequency are defined by the pins xpc[3:1]. For details refer to "Table 10 USB promer frequency settings". These settings are read at the beginning in the initialisation routine of the bootloader.
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Table 9 0 1 2 3 4 5 6 7
Boot definitions Chip version C22 Boot Device SPI master ST M25Pxx serial Nor Flash SPI master Atmel AT45DB011B serial Nor Flash SPI slave NandFlash IDE reserved for developers mode UART / Command Line Interface without diagnostics UART / Command Line Interface with diagnostics 000 001 010 011 100 101 110 111
XPC[3:1]
Table 10 USB promer frequency settings XPA[6:4] 000 001 010 011 100 others USB promer frequency settings 24 MHz 20 MHz 13 MHz 12 MHz 10 MHz reserved / defaults to 24 MHz
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5.2 AHB Peripheral Blocks
ARM AHB ("advanced high-performance bus") is the new generation of AMBA bus, which is intended to address the requirements of highperformance synthesizable designs. AMBA AHB implements the features required for high performance, high clock frequency systems including: * * * * * * burst transfers split transactions single cycle bus master handover non-tristate implementation 32 bit bus width the clock frequency of the AHB can set by software up to 65MHz
5.2.1 2.5 MBIT RAM Main Memory
The memory subsystem consists of a RAM part and a ROM part. Within the RAM memory subsystem, following functions are included: * * 1-TRAM controller with AHB bus slave interface 1-TRAM memory macros
5.2.1.1 1-TRAM Controller
The 1T RAM Controller is a slave interface connected to the AMBA AHB bus. * * * * slave AHB interface supports byte(8 bit), half-word(16 bit) and word(32 bit) read/write accesses 128-bit Line Buffer as temporary storage to reduce the number of memory accesses and optimise power consumption controls 5TSMC 1T-RAM instances
5.2.1.2 On-Chip 1T-RAM macro blocks
TSMC Emb1tRAMTM technology is a special kind of DRAM, which is implemented in a logic CMOS process. This innovative concept and design guarantees lowest power, high density, high performance and high yield advantages. ECC (Error Correction Code) technique is applied in the macro to dynamically correct errors caused by hard defects or soft errors. No fuses are needed because the conventional redundancy scheme is replaced with ECC design in the macro. The macro can be operated at clock rate from 20 MHz up to maximum AHB bus clock frequency in flow through random access mode. In the product, one idle cycle for refresh is needed in every 32 clock cycles. Total 5 macros with organisation of 4Kx128 = 64 KByte each are implemented. For the refresh, one master macro is generating the refresh clock (T1F4Kx128_PIFE) and four macros are connected serially in slave mode to the refresh clock (T1F4Kx128PIFES).
Features
* * * * * * * 20 Mhz to 65 Mhz operation speed Flow through random access Built-in error correction (ECC) 128-bit wide data bus Separated data in/out bus SRAM-style interface operation Built-in refresh controller with refresh clock generator
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5.2.2 On-Chip ROM
5.2.2.1 ROM Controller
The ROM controller implements the AHB slave interface for accessing the ROM. The ROM controller generates OK response for all reads and error response for all writes. Access width is always 32 bits.
5.2.2.2
1MBIT ROM
128 KByte of on-chip mask-programmable ROM are included. The ROM is metal mask programmable by a single mask change (VIA2). The ROM contains the following firmware package * Boot loader
5.2.2.3
* *
ROM versions and chip versions
There are two versions of the chip with changed Bootloader functionality available Version C21: Bootloader supports basic function for boot from external Nor Flash (ST or ATMEL). Version C22: Bootloader supports extended boot functions
These two chip versions differ only in the ROM content.
5.2.3 VIC - Vectored Interrupt Controller
The ARM PrimeCellTM PL190 "vectored interrupt controller" is included in the AHB system.
5.2.3.1
* * * * * * * * * * * *
Features
AMBA specification Rev 2.0 compliant support for 32 standard interrupts support for 16 vectored interrupts hardware interrupt priority IRQ and FIQ generation AHB mapped for fast interrupt response software interrupt generation test registers raw interrupt status interrupt request status interrupt masking privileged mode supportBlock Diagram
Figure 6 VIC Block Diagram
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5.2.3.2
IRQ Source 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VIC Interrupt Sources
Module Watchdog Timer 1 Timer 2 USB DMAC Nand Flash IDE MCI INTR0 MCI INTR1 AUDIO IRQ SSP I2C MS I2C Audio I2SIN I2SOUT UART IRQ Source 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Module GPIO4 (XPD) CGU Memory Stick DBOP GPIO1 (XPA) GPIO2 (XPB) GPIO3 (XPC)
Table 11 VIC Interrupt Sources
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5.2.4 SMDMAC - Single master DMAC
The ARM PrimeCellTM PL081 "SMDMAC single master DMA controller" is included in the AHB system. * * * * * * * * * AMBA specification Rev 2.0 compliant two DMA channels. Each channel can support a unidirectional transfer provides 16 peripheral DMA request lines single DMA and burst DMA request signals. Each peripheral connected to the PrimeCellTM SMDMAC can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the PrimeCellTM SMDMAC Memory-to-Memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral transfers. Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not need to occupy contiguous areas of memory Hardware DMA channel priority. Each DMA channel has a specific hardware priority. DMA channel 0 has the highest priority and channel 1 has the lowest priority. If requests from two channels become active at the same time the channel with the highest priority is serviced first. AHB slave DMA programming interface. The PrimeCellTM SMDMAC is programmed by writing to the DMA control registers over the AHB slave interface One AHB bus master for transferring data. This interface is used to transfer data when a DMA request goes active.
Figure 7 SMDMAC Block Diagram
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5.2.4.1
Table 12
DMAC Registers
DMAC Registers Base Address AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE AS3525_DMAC_BASE Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x020 0x024 0x028 0x02C 0x030 0x034 0x100 0x104 0x108 0x10C 0x110 0x120 0x124 0x128 0x12C 0x130 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Note Interrupt status register Interrupt terminal count status register Interrupt terminal count clear register Interrupt error status register Interrupt error clear register Raw interrupt terminal count status register Raw interrupt error status register Software burst request register Software single request register Software last burst request register Software last single request register Configuration register Synchronisation register Channel 0 source address Channel 0 destination address Channel 0 linked list item register Channel 0 control register Channel 0 configuration register Channel 1 source address Channel 1 destination address Channel 1 linked list item register Channel 1 control register Channel 1 configuration register peripheral ID0 register peripheral ID1 register peripheral ID2 register peripheral ID3 register peripheral cell ID0 register peripheral cell ID1 register peripheral cell ID2 register peripheral cell ID3 register
Register Name DMAC_IntStatus DMAC_IntTCStatus DMAC_IntTCClear DMAC_IntErrorStatus DMAC_IntErrorClear DMAC_RawIntTCStatus DMAC_RawIntErrorStatus DMAC_SoftBReq DMAC_SoftSReq DMAC_SoftLBReq DMAC_SoftSBReq DMAC_Configuration DMAC_Sync DMAC_C0SrcAddr DMAC_C0DestAddr DMAC_C0LLI DMAC_C0Control DMAC_C0Configuration DMAC_C1SrcAddr DMAC_C1DestAddr DMAC_C1LLI DMAC_C1Control DMAC_C1Configuration DMAC_PeripheralId0 DMAC_PeripheralId1 DMAC_PeripheralId2 DMAC_PeripheralId3 DMAC_CellId0 DMAC_CellId1 DMAC_CellId2 DMAC_CellId3
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5.2.5 Multi Port Memory Controller (MPMC)
The MPMC block is integrated into the AMBA system through AHB slave port. The PrimeCellTM MPMC offers: * AMBA 32-bit AHB compliance. * Dynamic memory interface support including SDRAM and JEDEC low-power SDRAM * Asynchronous static memory device support including RAM, ROM, and Flash, with or without asynchronous page mode. * Low transaction latency. * Read and write buffers to reduce latency and to improve performance. * Single AHB interface for accessing external memory. * 8-bit and 16-bit wide static memory support. * 16-bit wide chip select SDRAM memory support. * Static memory features include: * asynchronous page mode read * programmable wait states * bus turnaround delay * output enable, and write enable delays * extended wait * Two chip selects for synchronous memory and two chip selects for static memory devices. * Software controllable HCLK to MPMCCLKOUT ratio. * Power-saving modes dynamically control SDRAM MPMCCKEOUT and MPMCCLKOUT. * Dynamic memory self-refresh mode supported by software. * Controller supports 2K, 4K, and 8K row address synchronous memory parts. That is typical 512MB, 256MB, 128MB, and 16Mb parts, with 8, 16 bits per device. * Two reset domains enable dynamic memory contents to be preserved over a soft reset. * A separate AHB interface to program the MPMC. This enables the PrimeCellTM MPMC registers to be situated in memory with other system peripheral registers. * Locked AHB transactions supported. * Support for all AHB burst types. Figure 8 Multi Port Memory Controller Block Diagram
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5.2.6 IDE Interface
The IDE host interface core provides an efficient and easy-to-use interface to IDE and ATAPI devices. The core implements programmable I/O, Multi-word DMA, and Ultra ATA-33, -66, -100 and -133 modes of operation and supports up to two devices. The core interface to the system-on-chip provides PIO access and DMA capability to optimise data transfers to and from the IDE devices. For ease of integration, this interface includes a register set compatible with the Intel chip set, including a descriptor-based scatter-gather DMA core. This core is compatible with ATA-4 with Ultra ATA33, -66, -100 and -133 extensions. Single-word DMA is not supported. The licensed SpeedSelectTM technology allows the core to be reconfigured to support any timing mode for PIO, MultiWord DMA, and Ultra ATA transfers (-33, -66, -100 or -133) while running at any clock frequency. Interface to the host processor is the AMBA AHB bus architecture. There are two AHB interfaces on the core: an AHB master and an AHB slave.
5.2.6.1
AHB Master Interface
The AHB Master implements a subset of the AHB protocol. The following features are supported: * Single transfer, unspecified-length, 4-beat incrementing and optionally 8-beat incrementing bursts (HBURST will be `000', `001', `011', or optionally `101') * Accesses that cross a 1kB boundary will be unspecified-length incrementing (HBURST will be `001') * 16-bit and 32-bit transfers only (HSIZE will only be `001' or `010') * BUSY cycles are not issued (HTRANS will not be `01') * HPROT is not implemented * OKAY, SPLIT and RETRY responses accepted (HRESP may be `00', `10' or '11') * HLOCK asserted during fixed-length bursts * The AHB master may be granted by default
5.2.6.2
AHB Slave Interface
The AHB Slave implements a subset of the AHB protocol. The following features are supported: * Non-burst only (HBURST must be `000') * 8-, 16-, or 32-bit transfers only (HSIZE must be `000', `001' or `010') * No advantage is gained by issuing a SEQ cycle over a NONSEQ cycle (HTRANS values of `10' and `11' are interpreted identically) * HPROT is ignored * HRESP is `00' (OKAY) * HREADY is issued no sooner than 2 clock cycles after a valid SEQ or NONSEQ cycle * The AHB slave may be selected by default
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5.2.6.3
IDE Block diagram
Figure 9 IDE Block Diagram
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5.2.6.4
IDE Interface Registers
Table 13 IDE Interface Registers Register Name IdeReg_BMICP IdeReg_BMISP IdeReg_BMIDTPP_LO IdeReg_BMIDTPP_HI IdeReg_IDETIMP_LO IdeReg_IDETIMP_HI IdeReg_IDETIMS_LO IdeReg_IDETIMS_HI IdeReg_SIDETIM IdeReg_SLEWCTL_LO IdeReg_SLEWCTL_HI IdeReg_IDESTAT IdeReg_UDMACTL IdeReg_UDMATIM_LO IdeReg_UDMATIM_HI IdeReg_MISCCTL IdeReg_REGSTB IdeReg_REGRCVR IdeReg_DATSTB IdeReg_DATRCVR IdeReg_DMASTB IdeReg_DMARCVR IdeReg_UDMASTB IdeReg_UDMATRP IdeReg_UDMATENV IdeReg_IORDYTMP IdeReg_IORDYTMS IdeTaskF_DATA IdeTaskF_ERR_FEAT IdeTaskF_SECT_CNT IdeTaskF_SECT_NUM IdeTaskF_CYL_LO IdeTaskF_CYL_HI IdeTaskF_DEV_HEAD IdeTaskF_STAT_CMD IdeTaskF_ALT_STAT_DEV_CTRL IdeTaskF_DEV_ADDR Base Address AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE AS3525_CF_IDE_BASE Offset 0x00 0x02 0x04 0x06 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x4A 0x4B 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x1F0 0x1F1 0x1F2 0x1F3 0x1F4 0x1F5 0x1F6 0x1F7 0x3F6 0x3F7 Note primary channel bus master command primary channel bus master status primary channel bus master table pointer primary channel timing register secondary channel timing register slave IDE timing register slew rate control register IDE status register ultra DMA control register ultra DMA timing register miscellaneous control register task file register strobe timing register task file register recovery timing register data register PIO strobe timing register data register PIO recovery timing register DMA strobe timing register DMA recovery timing register ultra DMA strobe timing register ultra DMA ready-to-stop timing register ultra DMA timing envelope register primary IO ready timer configuration reg secondary IO ready timer configuration reg
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5.2.7 USB 2.0 HS OTG interface
The USB 2.0 on-chip interface includes the USB 2.0 On-The-Go Physical Interface and the HS OTG controller. Figure 10 USB 2.0 Interface
5.2.7.1
HS OTG controller subsystem
The Synopsys HS OTG subsystem is a configurable design. The HS OTG subsystem is fully compliant with the On-TheGo supplement to the USB 2.0 specification, Revision 1.0a. The subsystem supports high speed (480-Mbps) and fullspeed transfers. It is designed to interface to the AMBA AHB bus, shielding the application from the complexities of the HS OTG subsystem-native protocols and simplifying the system interface.
The OTG subsystem can be configured using application software as follows:
* * * * * * * * * * * * * * * * * * OTG dual-role device (DRD) OTG device only OTG mini host only * * * USB High-Speed (HS) device USB HS mini host USB Full-Speed (FS) device
The HS OTG subsystem has the following interfaces
the UTMI+, which connect the on-chip PHY to the HS OTG core the AHB slave interface, which provides the microcontroller with read and write access to the core's control and status register (CSRs) the AHB master interface, which enables the core to act as a master on the AHB to transfer data to and from the core's DMA controller the descriptor prefetch buffer RAM interface, which connects to an single-port RAM for DMA descriptor prefetch buffer storage the data RAM interface, which connects to and dual-port RAM (FIFO memory) for transaction data storage * * *
General features
handles all clock synchronisation within the core uses a descriptor prefetch buffer for optimal AHB use in host mode supports adaptive buffering for dynamic FIFO memory allocation, avoiding gaps in RAM utilisation SOFs are supported in high/full speed modes includes built-in DMA includes hardware transaction scheduling for enhanced performance supports memory mapped address space for the CSRs
USB 2.0 supported features
supports up to 15 configurations in Device mode * each configuration supports 15 interfaces * each interface handles up to 15 alternate settings supports session request protocol (SRP) supports session request protocol (SRP) supports Host Negotiation Protocol (HNP) recovers clock and data from the USB * * *
supports a generic root hub includes auto ping/split completion capabilities complies with UTMI+ level 3 interface
Implemented Controller configurations are:
configured with 4 host channels and 3 bidirectional- plus 1 in-endpoints in device mode dynamic alternate configuration selection (for different bandwidths of isochronous endpoints)
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5.2.7.2
* * * * * * *
USB 2.0 OTG PHY
*
Complete PHY for USB2.0 On-The-Go USB 2.0 UTMI+ specification compliant Supports high speed (480 Mbit/s), full speed (12 Mbit/s) and low speed (1.5 Mbit/s) data transmission Supports OT supplement features: VBUS state detecting SRP request by "data-line pulsing" method Low jitter clock from either on-chip PLL (48MHz) or optional additional crystal (12MHz, 24MHz or 48MHz) which is available with the 224 pin package, only 16 bit parallel datain/out interface Typical current consumption on vdda33c and vdd33t: * 12 mA in FS RX mode * 30 mA in FS TX mode * 30 mA in HS RX mode * 40 mA in HS TX mode * < 100 uA in suspend mode Rext = 3.4kOhm (+/- 1%) must be connected between pads "rext" and "vssa33c" to set the bias current.
5.2.7.3
USB 2.0 OTG Interface Registers
Table 14 USB Interface Registers Register Name USB_IEP0_CTRL USB_IEP0_STS USB_IEP0_TXFSIZE USB_IEP0_MPS USB_IEP0_DESC_PTR USB_IEP0_STS_MASK USB_IEP1_CTRL USB_IEP1_STS USB_IEP1_TXFSIZE USB_IEP1_MPS USB_IEP1_DESC_PTR USB_IEP1_STS_MASK USB_IEP2_CTRL USB_IEP2_STS USB_IEP2_TXFSIZE USB_IEP2_MPS USB_IEP2_DESC_PTR USB_IEP2_STS_MASK USB_IEP3_CTRL USB_IEP3_STS USB_IEP3_TXFSIZE USB_IEP3_MPS USB_IEP3_DESC_PTR USB_IEP3_STS_MASK USB_OEP0_CTRL USB_OEP0_STS USB_OEP0_RXFR USB_OEP0_MPS USB_OEP0_SUP_PTR USB_OEP0_DESC_PTR USB_OEP0_STS_MASK USB_OEP1_CTRL USB_OEP1_STS USB_OEP1_RXFR Base Address AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE Offset 0x00000 0x00004 0x00008 0x0000c 0x00014 0x00018 0x00020 0x00024 0x00028 0x0002c 0x00034 0x00038 0x00040 0x00044 0x00048 0x0004c 0x00054 0x00058 0x00060 0x00064 0x00068 0x0006c 0x00074 0x00078 0x00200 0x00204 0x00208 0x0020c 0x00210 0x00214 0x00218 0x00220 0x00224 0x00228 Note Control Register Status Register TxFIFO Size Maximum Packet Size Data Descriptor Pointer Status Mask Register Control Register Status Register TxFIFO Size Maximum Packet Size Data Descriptor Pointer Status Mask Register Control Register Status Register TxFIFO Size Maximum Packet Size Data Descriptor Pointer Status Mask Register Control Register Status Register TxFIFO Size Maximum Packet Size Data Descriptor Pointer Status Mask Register Control Status Register Rx Packet Frame Number Register RxFIFO Size/Maximum Packet Size Setup buffer Pointer Register Data Descriptor Pointer Status Mask Register Control Register Status Register Rx Packet Frame Number Register
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Register Name USB_OEP1_MPS USB_OEP1_SUP_PTR USB_OEP1_DESC_PTR USB_OEP1_STS_MASK USB_OEP2_CTRL USB_OEP2_STS USB_OEP2_RXFR USB_OEP2_MPS USB_OEP2_SUP_PTR USB_OEP2_DESC_PTR USB_OEP2_STS_MASK USB_OEP3_CTRL USB_OEP3_STS USB_OEP3_RXFR USB_OEP3_MPS USB_OEP3_SUP_PTR USB_OEP3_DESC_PTR USB_OEP3_STS_MASK USB_DEV_CFG USB_DEV_CTRL USB_DEV_STS USB_DEV_INTR USB_DEV_INTR_MASK USB_DEV_EP_INTR USB_DEV_EP_INTR_MASK USB_PHY_EP0_INFO USB_PHY_EP1_INFO USB_PHY_EP2_INFO USB_PHY_EP3_INFO USB_PHY_EP4_INFO USB_PHY_EP5_INFO USB_HOST_CH0_SPLT USB_HOST_CH0_STS USB_HOST_CH0_TXFSIZE USB_HOST_CH0_REQ USB_HOST_CH0_PER_INFO USB_HOST_CH0_DESC_PTR USB_HOST_CH0_STS_MASK USB_HOST_CH1_SPLT USB_HOST_CH1_STS USB_HOST_CH1_TXFSIZE USB_HOST_CH1_REQ USB_HOST_CH1_PER_INFO USB_HOST_CH1_DESC_PTR USB_HOST_CH1_STS_MASK USB_HOST_CH2_SPLT USB_HOST_CH2_STS USB_HOST_CH2_TXFSIZE USB_HOST_CH2_REQ USB_HOST_CH2_PER_INFO
Base Address AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE
Offset 0x0022c 0x00230 0x00234 0x00238 0x00240 0x00244 0x00248 0x0024c 0x00250 0x00254 0x00258 0x00260 0x00264 0x00268 0x0026c 0x00270 0x00274 0x00278 0x00400 0x00404 0x00408 0x0040c 0x00410 0x00414 0x00418 0x00504 0x00508 0x0050c 0x00510 0x00514 0x00518 0x01000 0x01004 0x01008 0x0100c 0x01010 0x01014 0x01018 0x01020 0x01024 0x01028 0x0102c 0x01030 0x01034 0x01038 0x01040 0x01044 0x01048 0x0104c 0x01050
Note RxFIFO Size/Maximum Packet Size Setup buffer Pointer Register Data Descriptor Pointer Status Mask Register Control Register Status Register Rx Packet Frame Number Register RxFIFO Size/Maximum Packet Size Setup buffer Pointer Register Data Descriptor Pointer Status Mask Register Control Register Status Register Rx Packet Frame Number Register RxFIFO Size/Maximum Packet Size Setup buffer Pointer Register Data Descriptor Pointer Status Mask Register Device Configuration Register Device Control Register Device Status Register Device Interrupt Register Device Interrupt Mask Register Device Endpoint Interrupt Device Endpoint Interrupt Mask Information Register Information Register Information Register Information Register Information Register Information Register Split Information Register Status Register TxFIFO Register Request Register Periodic/Split Transaction Information Register Data Descriptor Pointer Status Mask Register Split Information Register Status Register TxFIFO Register Request Register Periodic/Split Transaction Information Register Data Descriptor Pointer Status Mask Register Split Information Register Status Register TxFIFO Register Request Register Periodic/Split Transaction Information
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Register Name USB_HOST_CH2_DESC_PTR USB_HOST_CH2_STS_MASK USB_HOST_CH3_SPLT USB_HOST_CH3_STS USB_HOST_CH3_TXFSIZE USB_HOST_CH3_REQ USB_HOST_CH3_PER_INFO USB_HOST_CH3_DESC_PTR USB_HOST_CH3_STS_MASK USB_HOST_CFG USB_HOST_CTRL USB_HOST_INTR USB_HOST_INTR_MASK USB_HOST_CH_INTR USB_HOST_CH_INTR_MASK USB_HOST_FRAME_INT USB_HOST_FRAME_REM USB_HOST_FRAME_NUM USB_HOST_PORT0_CTRL_STS USB_OTG_CSR USB_I2C_CSR USB_GPIO_CSR USB_SNPSID_CSR USB_USERID_CSR USB_USER_CONF1 USB_USER_CONF2 USB_USER_CONF3 USB_USER_CONF4 USB_USER_CONF5
Base Address AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE AS3525_USB_BASE
Offset 0x01054 0x01058 0x01060 0x01064 0x01068 0x0106c 0x01070 0x01074 0x01078 0x01400 0x01404 0x0140c 0x01410 0x01414 0x01418 0x0141c 0x01420 0x01424 0x01500 0x02000 0x02004 0x02008 0x0200c 0x02010 0x02014 0x02018 0x0201c 0x02020 0x02024
Note Register Data Descriptor Pointer Status Mask Register Split Information Register Status Register TxFIFO Register Request Register Periodic/Split Transaction Information Register Data Descriptor Pointer Status Mask Register Host Configuration Register Host Control Register Host Interrupt Register Host Interrupt Mask Register Host Channel Interrupt Register Host Channel Interrupt Mask Register Host Frame Interval Register Host Frame Remaining Register Host Frame Number Register Host Port and Status Register OTG Control and Status Register I2C Access Register General Purpose Input/Output Register Synopsys ID Register User ID Register User Config1 Register User Config2 Register User Config3 Register User Config4 Register User Config5 Register
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5.2.8 Memory Stick / Memory Stick Pro Interface
The Sony memory stick interface is an AHB bus slave device. This interface conforms to following standards: * * Memory Stick Standard Format Specifications version 1.4-00 Memory Stick PRO Format Specifications version 1.00-01
5.2.8.1
Block Diagram
The memory stick interface contains two main blocks, the ICON and the host controller. Figure 12 SONY memory stick interface block diagram
5.2.8.2
I-CON
This IP is Memory Stick / Memory Stick PRO Host Controller automatic control IP with a 32-bit CPU interface. This IP automatically controls the series of TPC-based communication with the Memory Stick in place of the CPU, and aims to reduce the burden on the Host CPU. The contents of communication with the Memory Stick are designated in this IP by micro codes.
Features
* * * * * * 32-bit CPU interface Inside controller specified by microcodes Buffer for two-way data transmission loaded (256 byte x 2) 32/16 bit access available DMA support General-purpose data transmit/receive FIFO (12 Bytes)
5.2.8.3
Features
* * * * * *
Host Controller
Memory Stick and Memory Stick PRO support FiFo memory (64 bits x 4) for two-way data transmission Built-in CRC circuit Memory Stick serial clock (Serial: 20 MHz (max.), Parallel: 40 MHz (max.)) DMA support 16/32/64-bit access possible
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5.2.8.4 Functional description
Communication with the Memory Stick
The communication protocol with the Memory Stick is started by write from the CPU to the command register. When the protocol finishes, the CPU is notified that the protocol has ended by an interrupt request.
Data transfer request
When the protocol is started and enters the data transfer state, data is requested by issuing a DMA transfer request or an interrupt request to the CPU. Data can also be requested to an external memory.
Memory Stick communication time out
The RDY time out time when the handshake state (read protocol: BS2, write protocol: BS3) is established in communication with the Memory Stick can be designated as the number of Memory Stick transfer clocks. When a time out occurs, the CPU is notified that the protocol has ended due to a time out error by an interrupt request.
CRC off
CRC off can be set as a test mode. When CRC off is set, CRC is not added to the data transmitted to the Memory Stick.
PAD cells
The connections to the MemoryStick Interface are shared with the General Purpose I/O port-D (GPIO xpd[0:7]). Figure 13 external memory stick connection
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5.3
APB Peripheral Block
5.3.1 Timers
The Dual Input Timers module is an APB slave that provides access to two interrupt-generating, programmable 32-bit free-running decrementing counters (FRCs). The system clock (PCLK) is used to control the programmable registers, and the second clock input is used to drive the counter, enabling the counters to run from a much slower clock than the system clock. This input clock of the counters (TIMCLK) is connected to a clock derived (divided by 16) from the main clock (clk_main) signal. That clock clk_main is always running and is coming from the internal or external oscillator (set by clk_sel pad).
5.3.1.1 Timer modes
* * * Free-running mode: the counter wraps after zero and continues at the maximum value. This is the default mode. Periodic mode: reload of original value after wrapping past zero. One-shot mode - interrupt is generated once, counter halts after reaching zero
Figure 14 Timer Block Diagram
Each timer has an identical set of registers shown in table Table 15. The operation of each timer is identical. The timer is loaded by writing to the load register and, if enabled, counts down to zero. When a counter is already running, writing to the load register will cause the counter to immediately restart at the new value. Writing to the background load value has no effect on the current count. The counter continues to decrement to zero, and then recommences from the new load value (if in periodic mode, and one shot mode is not selected). When zero is reached, an interrupt is generated. The interrupt can be cleared by writing to the clear register. If One Shot Mode is selected, the counter halts on reaching zero One Shot Mode is deselected, or a new load value is written. Otherwise, after reaching a zero count, if the timer is operating in free-running mode it continues to decrement from its maximum value. If periodic timer mode is selected, the timer reloads the count value from the load register and continues to decrement. In this mode the counter effectively generates a periodic interrupt. The mode is selected by a bit in the timer control register. At any point, the current counter value can be read from the value register. The counter is enabled by a bit in the control register. At reset, the counter is disabled, the interrupt is cleared, and the load register is set to zero. The mode and prescale values are set to free-running, and clock divide of 1 respectively.
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The timer clock enable is generated by a prescale unit. The enable is then used by the counter to create a clock with a timing of one of the following. * * * The system clock The system clock divided by 16, generated by 4 bits of prescale The system clock divided by 256, generated by a total of 8 bits of prescale
Figure 15 - timer prescaler
5.3.1.2 Interrupt generation
An interrupt is generated when the full 32-bit counter reaches zero, and is only cleared when the TimerXClear location is written to. A register holds the value until the interrupt is cleared. The most significant carry bit of the counter detects the counter reaching zero. Interrupts can be masked by writing 0 to the interrupt enable bit in the control register. Both the raw interrupt satus (prior to masking) and the final interrupt status (after masking) can be read from status registers. Timer 1 interrupt output is connected to interrupt input line irq1 (VIC input) and Timer 2 interrupt output is connected to interrupt line irq2.
5.3.1.3 Timer Register Descriptions
Table 15 - Timer 1 and 2 registers Register Name Timer1Load Timer1Value Timer1Control Timer1IntClr Timer1RIS Timer1MIS Timer1BGLoad Timer2Load Timer2Value Timer2Control Timer2IntClr Timer2RIS Timer2MIS Timer2BGLoad Periheral ID register bits 7:0 Periheral ID register bits 15:8 Periheral ID register bits 23:16 Periheral ID register bits 31:24 Primecell ID register bits 7:0 Primecell ID register bits 15:8 Primecell ID register bits 23:16 Primecell ID register bits 31:24 Base Address AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE AS3525_TIMER_BASE Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Note load value for Timer 1 current value for Timer 1 Timer 1 control register Timer 1 interrupt clear Timer 1 raw interrupt status Timer 1 masked interrupt status Timer 1 background load value load value for Timer 2 current value for Timer 2 Timer 2 control register Timer 2 interrupt clear Timer 2 raw interrupt status Timer 2 masked interrupt status Timer 2 background load value Peripheral ID register bits 7:0 Peripheral ID register bits 15:8 Peripheral ID register bits 23:16 Peripheral ID register bits 31:24 Primecell ID register bits 7:0 Primecell ID register bits 15:8 Primecell ID register bits 23:16 Primecell ID register bits 31:24
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Load register, Timer1Load, Timer2Load
This is a 32-bit register containing the value from which the counter is to decrement. This is the value used to reload the counter when periodic mode is enabled, and the current count reaches zero. When this register is written to directly, the current count is immediately reset to the new value at the next rising edge of TIMCLK which is enabled by TIMCLKEN. The value in this register is also overwritten if the TimerXBGLoad register is written to, but the current count is not immediately affected. If values are written to both the timerXLoad and TimerXBGLoad registers before an enabled rising edge on TIMCLK, the following occurs: * On the next enabled TIMCLK edge the value written to the TimerXLoad value replaces the current count value * Following this, eacht time the counter reaches zero, the current count value is reset to the value written to TimerXBGLoad. Reading from the TimerXLoad register at any time after the two writes have occurred will retrieve the value written to TimerXBGLoad. That is, the value read from TimerXLoad is always the value which will take effect for periodic mode after the next time the counter reaches zero.
Current value register, Timer1Value, Timer2Value
This register gives the current value of the decrementing counter.
Timer control register
Table 16 Timer control register Name Timer1Control, Timer2Control Offset: 0x08, 0x28 Bit 7 Bit Name Timer Enable Base AS3525_TIMER_BASE Default 0x20
Timer Control Register Contains control bits of the PLLA register. Default 0 Access R/W Bit Description Enable bit: 0: timer disabled (default) 1: timer enabled Mode bit 0: timer is in free-running mode (default) 1: timer is in periodic mode Interrupt enable bit 0: timer interrupt disabled 1: timer interrupt enabled (default) Reserved bit, do not modify, and ignore on read Prescale bits: 00: no prescale, clock is divided by 1 (default) 01: 4 stages of prescale, clock is divided by 16 10: 8 stages of prescale, clock is divided by 256 11: undefined, do not use Selects 16/32 bit counter operation 0: 16 bit counter (default) 1: 32 bit counter Selects one-shot or wrapping counter mode 0: wrapping mode (default) 1: one-shot mode
6
Timer Mode
0
R/W
5
Interrupt Enable
1
R/W
4 3:2
RESERVED TimerPre
00
R/W
1
Timer Size
0
R/W
0
OneShotCount
0
R/W
Interrupt clear register, Timer1IntClr, Timer2IntClr
Any write to this register will clear the interrupt output from the counter
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Raw Interrupt status register, Timer1RIS, Timer2RIS
This register indicates the raw interrupt status from the counter. This value is ANDed with the timer interrupt enable bit from the control register to create the masked interrupt, which is passed to the interrupt output pin. Table 17 raw interrupt status register Name Timer1RIS, Timer2RIS Offset: 0x10, 0x30 Bit 0 Bit Name Raw Timer Interrupt Base AS3525_TIMER_BASE Default
Timer raw interrupt status register Contains control bits of the PLLA register. Default Access R Bit Description Raw interrupt status from the counter
Interrupt status register, TIMERXMIS
This register indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the timer interrupt enable bit from the control register, and is the same value which is passed to the interrupt output pin. Table 18 interrupt status register Name Timer1MIS, Timer2MIS Offset: 0x10, 0x30 Bit 0 Bit Name Raw Timer Interrupt Base AS3525_TIMER_BASE Default
Timer raw interrupt status register Contains control bits of the PLLA register. Default Access R Bit Description Raw interrupt status from the counter
Background load register, TimerXBGLoad
This is a 32 bit register containing the value from which the counter is to decrement. This is the value used to reload the counter when periodic mode is enabled, and the current count reaches zero. This register privides an alternative method of accessing the TimerXLoad register. The difference is that writes to TimerXBGLoad will not cause the counter immediately to restart from the new value. Reading from this register returns the same value returned from TimerXLoad.
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5.3.2 Watchdog Unit
The watchdog unit provides a way of recovering from software crashes. The watchdog clock is used to generate a regular interrupt (WDOGINT), depending on a programmed value. The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt remains unserviced for the entire programmed period. You can enable or disable the watchdog unit as required. Clock reference for the watchdog is PCLK divided by 256. Figure 16 watchdog unit
5.3.2.1
Watchdog register descriptions
Table 19 Watchdog Registers Register Name WDT_LOAD WDT_VALUE WDT_CONTROL WDT_INTCLR WDT_RIS WDT_MIS WDT_LOCK WDT_PERIPHID0 WDT_PERIPHID1 WDT_PERIPHID2 WDT_PERIPHID3 WDT_PCELLID0 WDT_PCELLID1 WDT_PCELLID2 WDT_PCELLID3 Base Address AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE AS3525_WDT_BASE Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0xC00 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Note load register counter current value control register Interrupt clear register Raw interrupt status register Masked interrupt status register Lock register Watchdog peripheral ID 0 register Watchdog peripheral ID 1 register Watchdog peripheral ID 2 register Watchdog peripheral ID 3 register Watchdog primecell ID 0 register Watchdog primecell ID 1 register Watchdog primecell ID 2 register Watchdog primecell ID 3 register
Watchdog load register, WdogLoad
This is a 32-bit register containing the value from which the counter is to decrement. When this register is written to, the count is immediately restarted from the new value. The minimum valid value for WdogLoad is one.
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Watchdog control register, WdogControl
This is a read/write register that enables the software to control the watchdog unit. Table 20 watchdog control register Name WdogControl Offset: 0x08 Bit 1 Bit Name RESEN Default 0 Access R/W Base AS3525_WDT_BASE Watchdog Control Register Bit Description Enable Watchdog reset output (WDOGRES). Acts as a mask for the reset output. 0: disable the reset 1: enable the reset Enable the interrupt event (WDOGINT). 0: disable the counter and interrupt 1: enable the counter and interrupt Default 0x04
0
INTEN
0
R/W
Watchdog clear interrupt register, WdogIntClr
A write of any value to this location clears the watchdog interrupt, and reloads the counter from the value in WdogLoad.
Raw interrupt status register, WdogRIS
This register indicates the raw interrupt status from the counter. This value is ANDed with the inerrupt enable bit from the control register to create the masked interrupt, which is passed to the interrupt output pin. Table 21 watchdog raw interrupt status register Name WdogRIS Offset: 0x10 Bit 0 Bit Name Watchdog Interrupt Default Access R Base AS3525_WDT_BASE Watchdog interrupt status register Bit Description Enabled interrupt status from the counter Default
Interrupt status register, WdogMIS
This register indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the INTEN bit from the control register, and is the same value which is passed to the interrupt output pin. Name WdogMIS Offset: 0x14 Bit 0 Bit Name Raw Watchdog Interrupt Default Access R Base AS3525_WDT_BASE Watchdog raw interrupt status register Bit Description Raw interrupt status from the counter Default
Table 22 watchdog interrupt status register
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Watchdog lock register, WdogLock
Use of this register allows write-access to all other registers to be disabled. This is to prenent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 will enable write access to all other registers. Writing any other value will disable write accesses. A read from this register will return only the bottom bit: * * 0 indicates that write access is enabled (not locked) 1 indicates that write access is disabled (locked)
Table 23 watchdog lock register Name WdogLock Offset: 0xC00 Bit 31:0 0 Bit Name Enable register writes Register write enable status Default Access W R Base AS3525_WDT_BASE Default 0x00
Watchdog raw interrupt status register Bit Description Enable write access to all other registers by writing 0x1ACCE551. Disable write access by writing any other value. 0: write access to all other registers is enabled (default) 1: write access to all other registers is disabled
0
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5.3.3
SSP - Synchronous Serial Port
The SSP is a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following: * a Motorola SPI-compatible interface * a TI synchronous serial interface * a National Semiconductor MicroWire interface * In both master and slave configurations the SSP performs * parallel-to-serial conversion on data written to an internal 16-bit wide, 8-location deep transmit FIFO * serial-to-parallel conversion on received data, buffering it in a similar 16-bit wide, 8 location-deep receive FIFO Interrupts are generated to: * request servicing of the transmit and receive FIFO * inform the system that a receive FIFO overrun has occurred * inform the system that data is present in the receive FIFO after an idle period has expired SSP Features: * compliant to AMBA Rev 2.0 * master or slave operation * programmable clock bit rate and prescale * separate receive and transmit memory buffers each 16 bits wide and 8 bits deep * programmable data frame size from 4 to 16 bit * independent masking of receive FIFO, transmit FIFO and receive overrun interrupts * internal loopback testmode available * support for DMA * identification register uniquely identifying the PrimeCellTM itself (support for OS) SPI features: * full-duplex, four wire synchronous transfer * programmable clock polarity and phase MicroWire features: * half duplex transfer using 8 bit control message Texas Instruments SSI features: * full-duplex, four wire synchronous transfer * transmit data PIN tristateable when not transmitting Programmable parameters: * master or slave mode * enabling of operation * frame format * communication baud rate * clock phase and polarity * data width from 4 to 16 bit * interrupt masking
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Table 24 SSP Registers Register Name SPI_SSPCR0 SPI_SSPCR1 SPI_SSPRXD SPI_SSPTXD SPI_SSPSR SPI_SSPCPSR SPI_SSPIMSC SPI_SSPIRS SPI_SSPMIS SPI_SSPICR SPI_SSPDMACR Base Address SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE SSP_BASE Offset 0x00 0x04 0x08 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 Note CR0 control register CR1 control register Read Data Register Write Data register SSP status register SSP Pre-scaler register SSP Interrupt Mask and clear register SSP Raw interrupt status register SSP Masked interrupt status register SSP interrupt clear register SSP DMA control register
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5.3.4 GPIO - General purpose input/output ports
The ARM PrimeCellTM PL061 "General Purpose Input/Output" is included in the APB system. * * * * * * compliant to AMBA Rev 2.0 each port has eight individually programmable input/output pins, default to input at reset four ports A, B, C, D are included programmable interrupt generation capability, from a transition or level condition, on any number of PINs hardware control capability of GPIO's for different system configurations. bit masking in both read and write operations through address lines
Figure 18 GPIO Block Diagram
Table 25: GPIO Registers Register Name GPIO1_DATA GPIO1_DIR GPIO1_IS GPIO1_IBE GPIO1_IEV GPIO1_IE GPIO1_RIS GPIO1_MIS GPIO1_IC GPIO1_AFSEL GPIO2_DATA GPIO2_DIR GPIO2_IS GPIO2_IBE GPIO2_IEV GPIO2_IE GPIO2_RIS GPIO2_MIS GPIO2_IC GPIO2_AFSEL Base Address AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE AS3525_GPIO2_BASE Offset 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 Note data register data direction register interrupt sense register interrupt both edges register interrupt event register interrupt mask register raw interrupt status masked interrupt status interrupt clear mode control select data register data direction register interrupt sense register interrupt both edges register interrupt event register interrupt mask register raw interrupt status masked interrupt status interrupt clear mode control select
44 - 124
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
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AS3524 C21 / C22 Data Sheet, Confidential Register Name GPIO3_DATA GPIO3_DIR GPIO3_IS GPIO3_IBE GPIO3_IEV GPIO3_IE GPIO3_RIS GPIO3_MIS GPIO3_IC GPIO3_AFSEL GPIO4_DATA GPIO4_DIR GPIO4_IS GPIO4_IBE GPIO4_IEV GPIO4_IE GPIO4_RIS GPIO4_MIS GPIO4_IC GPIO4_AFSEL Base Address AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE AS3525_GPIO4_BASE Offset 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C 0x420
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Note data register data direction register interrupt sense register interrupt both edges register interrupt event register interrupt mask register raw interrupt status masked interrupt status interrupt clear mode control select data register data direction register interrupt sense register interrupt both edges register interrupt event register interrupt mask register raw interrupt status masked interrupt status interrupt clear mode control select
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
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5.3.5 MCI - SD / MMC Card Interface
Features
* * * Conformance to Multimedia Card Specification v2.11 Conformance to Secure Digital Memory Card Physical Layer Specification, v0.96 uses multimedia card bus or SD card bus.
The PrimeCellTM MCI provides an interface between the APB system bus and multimedia and/or secure digital memory cards. It consists of two parts: * * The PrimeCellTM MCI adapter block includes the clock generation unit, the power management control, command and data transfer the APB interface provides access to the MCI adapter registers, and generates interrupt and DMA request signals.
Figure 19 Multimedia Card Interface Block Diagram
The connections to the Multimedia Card Interface are shared with the General Purpose I/O port-D (GPIO xpd[0:7]). Following diagram shows the external circuit elements for connection to a SD card adapter. Note that a feedback clock must be routed back to xpd[6]/mci_fbclk.
Figure 20 Connecting SD / MC to GPIO-D
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5.3.6 I2cAudMas - I2C audio master interface
This is the control interface between the digital and the audio-part. The corresponding signal lines are connected inside of the MCM on the BGA substrate. For test purposes of the audio chip only, the signals are available at dedicated balls. * * * * * * * * * * * The key features of this interface block are: serial 2-wire I2C bus master supports standard (100 kbps) and fast speed (400kbps) 7-bit addressing sub-addressing programmable clock divider programmable transfer count soft reset bit interrupt generation (on RX Full, TX Empty, RX Overrun, no acknowledge received) status register test register
Figure 21 I2C Audio Master Interface Block Diagram
Table 26 I2C Audio Master Registers Register Name I2C2_DATA I2C2_SLAD0 I2C2_CNTRL I2C2_DACNT I2C2_CPSR0 I2C2_CPSR1 I2C2_IMR I2C2_RIS I2C2_MIS I2C2_SR I2C2_INT_CLR I2C2_SADDR I2C2_TESTIN I2C2_TESTOUT1 I2C2_TESTOUT2 Base Address AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE AS3525_I2C_AUDIO_BASE Offset 0x00 0x04 0x0C 0x10 0x1C 0x20 0x24 0x28 0x2C 0x30 0x40 0x44 0x50 0x54 0x58 Note transmit/receive FIFO data register slave ID register control register master data count register clock prescale register 0 clock prescale register 1 interrupt mask register raw interrupt status register masked interrupt status register I2C status register interrupt clear register sub-address register test register (monitors state of SCL and SDA) test mode register for driving output interrupt test mode register for driving SCLout, SCLOEn, SDAOUT and SDAOEN signals
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5.3.7 I2CMSI - I2C master/slave interface
This is a general control interface for chip-to-chip communication. The corresponding IOs are either used by the general purpose port C (xpc[6:7]) or by this I2C interface. The features of this interface block are: * * * * * * * * * * serial 2-wire I2C bus master supports standard (100 kbps) and fast speed (400kbps) supports multi-master system architecture programmable clock divider programmable transfer count programmable slave wait enable (for slave mode of operation, insertion of wait on the bus) soft reset bit interrupt generation (on RX Full, TX Empty, RX Overrun, no acknowledge received) status register test register
Figure 22: I2C Interface
Table 27 I2C Interface Registers Register Name I2C1_DATA I2C1_SLAD0 I2C1_SLAD1 I2C1_CNTRL I2C1_DACNT I2C1_SEAD0 I2C1_SEAD1 I2C1_CPSR0 I2C1_CPSR1 I2C1_IMR I2C1_RIS I2C1_MIS I2C1_SR I2C1_TXCNT I2C1_RXCNT I2C1_TX_FLUSH I2C1_INT_CLR I2C1_TESTIN I2C1_TESTOUT1 I2C1_TESTOUT2 Base Address AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE AS3525_I2C_MS_BASE Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x50 0x54 0x58 Note transmit/receive FIFO data register slave ID register 0 slave ID register 1 control register master data count register self ID of slave 0 self ID of slave 1 clock prescale register 0 clock prescale register 1 interrupt mask register raw interrupt status register masked interrupt status register I2C status register transmit Fifo data count register receive Fifo data count register TX Fifo flush register interrupt clear register test register (monitors state of SCL and SDA) test mode register for driving output interrupt test mode register for driving SCLout, SCLOEn, SDAOUT and SDAOEN signals
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5.3.8 I2SIN - I2S input interface
The I2S input interface module (called I2SINIF module hereafter) is used to connect an external audio source to the processor system. The communication is based on the standardized I2S interface. The interface module connects to the processor system using the AMBA APB bus. All the input left & right channel data are mapped to either 14 or 24 bit format, selectable within the control register. If the data word length is less than 24 bit, the unused lower bits are set to zero. To reduce the interrupt frequency for the processor, a FIFO buffer is provided. The buffer can hold up to 32 words of 48 bit length (left plus right channel). Generation of interrupt request signal with several maskable interrupt sources (Pop Full, Pop Empty, Pop Error, Push Error, ...etc) The I2SINIF provides the following features: * two independent clock domains: AMBA APB clock PCLK, I2S input clock i2si_sclk * FIFO (32 words/48 bit) separating clock domains * support of several oversampling rates: 128x, 256x, 512x * interrupt support for FIFO data read * DMA support for FIFO data transfer The I2SINIF provides five different modes: * input from on-chip audio ADC * input from external audio ADC in master mode (SCLK, LRCK generated by external ADC) * input from external audio ADC in slave mode (SCLK, LRCK, MCLK generated internally and fed to external ADC) * input from SPDIF (SPDIF to I2S converter) * feedback mode with input from I2S output interface: used for test purposes
Figure 23 I2S Input Interface
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5.3.8.1
I2S Input Register Mapping
I2S Input Interface Registers
Table 28 I2S Input Interface Registers Base Address AS3525_I2SIN_BASE AS3525_I2SIN_BASE AS3525_I2SIN_BASE AS3525_I2SIN_BASE AS3525_I2SIN_BASE AS3525_I2SIN_BASE AS3525_I2SIN_BASE Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 Control register Interrupt mask register Raw status register Status register Interrupt clear register Audio data register SPDIF status signals register Note
Register Name I2SIN_CONTROL I2SIN_MASK I2SIN_RAW_STATUS I2SIN_STATUS I2SIN_CLEAR I2SIN_DATA I2SIN_SPDIF_STATUS
Table 29 I2S Input Control Register Name I2SIN_CONTROL Offset: 0x0000 Bit 11 Bit Name DMA_req_en Base AS3525_I2SIN_BASE Default 0x04
Control register 12 bit wide read/write register containing the control bits of the I2SINIF. Default 0 Access R/W Bit Description DMA request enable 0: disable 1: enable Invert MCLK 0: disable (SCLK changes at MCLK's falling edge) 1: enable (SCLK changes at MCLK's rising edge) Define the source of SCLK and LRCK for I2SINIF 00: SCLK and LRCK from I2SOUTIF (used if AFE sends data) 01: SCLK and LRCK from external ADC device (outside AS3525) 10: SCLK and LRCK from SPDIF converter 11: SCLK and LRCK from I2SINIF's clock controller Define the source of SDATA for I2SINIF 00: SDATA from AFE 01: SDATA from external ADC device (outside AS3525) 10: SDATA from SPDIF converter 11: loopback SDATA from I2SOUTIF (test purpose) 0: ADC data from FIFO transferred in two 32-bit words to I2SIN_DATA (first left and then right data as indicated by the stereo24_status bit) 1: ADC data from FIFO transferred in one 32-bit word to I2SIN_DATA Enable/disable SCLK for I2SINIF 0: SCLK enabled 1: SCLK disabled 0: SDATA ignored at first SCLK edge (I2S standard) 1: valid SDATA at first SCLK edge 0: data valid at negative edge of SCLK 1: data valid at positive edge of SCLK Oversampling rate (needed for generating sclk and lrck) 00: 128x 01: 256x 10: 512x 11: 128x
10
mclk_invert
0
R/W
9,8
i2s_clk_source
00
R/W
7,6
sdata_source
00
R/W
5
14bit_mode
0
R/W
4
sclk_idle
0
R/W
3 2 1,0
SDATA_valid sclk_edge osr
0 1 00
R/W R/W R/W
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The following table shows the valid combinations for sdata_source (bit 7 and 6) and i2s_clk_source (bit 9 and 8) of the I2SIN_CONTROL register. sdata_source 00 01 01 10 11 00 00 11 10 00 i2s_clk_source Description default mode (AFE with AS3525) external data, external clock external data, internal clock data and clock from SPDIF converter loopback, internal data and clock
Table 30 I2S Input mask register Name I2SIN_MASK Offset: 0x0004 Bit 7 6 5 4 3 2 1 0 Bit Name reserved I2SIN_MASK_PUER I2SIN_MASK_POE I2SIN_MASK_POAE I2SIN_MASK_POHF I2SIN_MASK_POAF I2SIN_MASK_POF I2SIN_MASK_POER Base AS3525_I2SIN_BASE Default 0x00
Interrupt mask register The interrupt mask register determines which status flags generate an interrupt by setting the corresponding bit to 1. Default 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit Description stereo24_status cannot assert interrupt request 1 enables the FIFO PUSH error interrupt 1 enables the FIFO POP is empty interrupt 1 enables the FIFO POP is almost empty interrupt 1 enables the FIFO POP is half full interrupt 1 enables the FIFO POP is almost full interrupt 1 enables the FIFO POP is full interrupt 1 enables the FIFO POP error interrupt
Table 31 I2S Input raw status register Name I2SIN_RAW_STATUS Base AS3525_I2SIN_BASE Default 0x00
Offset: 0x0008
Raw status register The read-only raw status register contains the actual bit values as reflected by the FIFO controller status signals. I2SIN_PUER and I2SIN_POER are static bits, since FIFO controller gives the PUSH/POP error bit only for one clock. This means that these two bits remain asserted until they are cleared in the I2SIN_CLEAR register. All other bits change state depending on the underlying logic, i.e. state of FIFO controller. Default 0 Access R Bit Description Status of write interface for 24 bit stereo mode 0: left audio sample will be transferred next 1: right audio sample will be transferred next 1 if FIFO PUSH error 1 if FIFO POP is empty 1 if FIFO POP is almost empty 1 if FIFO POP is half full 1 if FIFO POP is almost full 1 if FIFO POP is full 1 if FIFO POP error
Bit 7
Bit Name stereo24_status
6 5 4 3 2 1 0
I2SIN_PUER I2SIN_POE I2SIN_POAE I2SIN_POHF I2SIN_POAF I2SIN_POF I2SIN_POER
0 0 0 0 0 0 0
R R R R R R R
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AS3524 C21 / C22 Data Sheet, Confidential Table 32 I2S input status register Name I2SIN_STATUS Base AS3525_I2SIN_BASE
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Default 0x00
Offset: 0x000C
Status register The status register is a read-only register. A read to this register returns the value of the raw status bits AND'ed with the corresponding mask of enable bits set in the mask register. Default 0 Access R Bit Description Status of write interface for 24 bit stereo mode 0: left audio sample will be transferred next 1: right audio sample will be transferred next 1 if FIFO PUSH error 1 if FIFO POP is empty 1 if FIFO POP is almost empty 1 if FIFO POP is half full 1 if FIFO POP is almost full 1 if FIFO POP is full 1 if FIFO POP error
Bit 7
Bit Name stereo24_status
6 5 4 3 2 1 0
I2SIN_PUER I2SIN_POE I2SIN_POAE I2SIN_POHF I2SIN_POAF I2SIN_POF I2SIN_POER
0 0 0 0 0 0 0
R R R R R R R
Table 33 I2S Input interrupt clear register Name I2SIN_CLEAR Base AS3525_I2SIN_BASE Default 0x00
Offset: 0x0010
Interrupt clear register The interrupt clear register is a write-only register. The corresponding static status bit can be cleared by writing a 1 to the corresponding bit in the clear register. All other interrupt flags are level interrupts depending on the status of the FIFO. The bits are de-asserted depending on the FIFO controller. Default Access W W W W Bit Description Clear PUSH error interrupt flag Clear POP error interrupt flag
Bit 7 6 5:1 0
Bit Name reserved I2SIN_clear_puer reserved I2SIN_clear_poer
I2SIN_DATA
The I2SINIF provides a single 32 bit wide data register. The register is used to read the audio samples from FIFO. If 14 bit mode is selected, both the left and right data are made available in the same register. Otherwise in the 24 bit mode the left and right data are provided through the same register alternatively. The stereo24_status bit in the I2SIN_STATUS register provides information which channel's data will be provided next. The 14bit_mode bit in the I2SIN_CONTROL register defines how the values are read from the FIFO.
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5.3.8.2 I2S Input Signals
The following specifications signals are given: * * Data are valid at rising/falling edge of SCLK (depending on I2SI_CONTROL's setting). The left and right channels are indicated by the LRCK signal.
The timing diagram of the standard I2S interface signals from the ADC is shown below (Figure 27). Figure 24 - I2S standard timing diagram
Tperiod(fsaudio) / 2 Tperiod(fsaudio) / 2
LRCK SCLK SDATA
24 bit
Left Channel
Right Channel
X
23
2
1
0
X
23
2
1
0
While the I2S standard states that the LRCK line changes one clock cycle before the MSB is transmitted. If the ADC sends the MSB directly after LRCK line changes, the SDATA_valid bit in the I2SI_CONTROL register must be set.
Figure 25 - I2S standard timing diagram with SDATA valid directly after LRC changes
Tperiod(fsaudio) / 2 Tperiod(fsaudio) / 2
LRCK SCLK SDATA
24 bit
Left Channel
Right Channel
23
22
2
1
0
23
22
2
1
0
Assumption: The LRCK toggles every 32 clocks of SCLK.
5.3.8.3 Power Modes
The I2SINIF contains two clock domains. The PCLK domain can be turned off in the clock controller. The SCLK clock domain can be turned off locally using the SCLK_idle bit in the I2SIN_CONTROL register. Note that the SCLK's clock gating signal has to be synchronized with the SCLK clock in order to guarantee correct operation. If PCLK is turned off, no interrupt must be triggered by the I2SINIF module. The I2SI_MCLK clock can be turned on/off in the clock generation unit.
5.3.8.4 Loopback Feature
On the AS3525 are two I2S interfaces: I2SOUTIF is responsible to send values to the DAC of the audio chip via I2SO_SDATA I2SINIF is responsible to receive audio values from ADC of the audio chip via I2SI_SDATA In the AS3525 both SDATA signals are provided as loopback signals (I2SO_FSDATA, I2SI_FSDATA): I2SO_SDATA to I2SINIF: This loopback is mainly for testing the transmit and receive paths of both I2S interfaces. The loopback signal is called I2SO_FSDATA. I2SI_SDATA to I2SOUTIF: This loopback feature allows the application to echo the input audio samples directly to a loudspeaker. The signal provided by the I2SINIF is called I2SI_FSDATA. In normal mode the I2SINIF pushes audio values into the FIFO based on the I2SI_SDATA signal. If the loopback feature is enabled, the sdata_source bit in the control register must be set to 3. The FIFO content is filled with audio values send by the I2SOUTIF (signal I2SO_FSDATA). NOTE: This feature will only be available if SCLK is the same for I2S input and output interface. For implementation the I2SO_FSDATA signal is simply routed through a multiplexer to the I2SI_SDATA interface.
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5.3.8.5 DMA Interface
The I2SINIF supports DMA transfers. The DMA controller supports incrementing and non-incrementing (single address) addressing for source and destination. For I2SINIF the single-address mode is used. The address of the I2SI_DATA register is used as DMA source address.
5.3.8.6 The 24 bit Stereo DMA Mode
In 24 bit stereo mode, right and left audio samples must be read separately from the FIFO. In single-address DMA-mode both data must be read from the same address. The I2SINIF is responsible to split up the 48 bit FIFO entries into two 24 bit samples. The 24 bit value can then be transferred via the 32 bit wide AMBA bus. The I2SINIF provides the data in a specific order: first the left value is sent, and afterwards the right value is provided. Then a left value follows, and so on. In the destination memory the words are stored incrementally as shown below. Address addr 0 addr 1 addr 2 addr 3 ... addr n*2 addr n*2+1 LDATA 0 RDATA 0 LDATA 1 RDATA 1 ... LDATA n RDATA n Value
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5.3.9 SPDIF interface
As part of the I2SIN module also a SPDIF receiver interface is included. This SPDIF interface works as converter from SPDIF-AES/EBU to I2S. The SPDIF-AES/EBU standard is a serial audio interface that conveys 2 time-multiplexed audio channels, the left and right channels, as is the case in audio stereo transmission. The two channels are encoded in a 64-bit frame. Each individual channel is encoded in a sub-frame that consists of a 4-bit preamble, followed by 24 bits of audio data and 4 control bits, in a total of 32 bits per sub-frame. The SPDIF-AES/EBU standard provides for LSB first, up to 24-bit audio samples, Samples of 20 bits or less may be used, in which case the 4 least significant bits may be used for a 12-bit monitoring channel, transmitted at 1/3 of the sample rate. Please refer to the SPDIF-AES/EBU, AES3 or IEC958 standard documentation for more information.
Features
* * * * * Feed-forward operation: extracts audio data from the SPDIF-AES/EBU input signal by sampling it with a fast clock signal which not necessarily related to the sample rate frequency Purely digital receiver solution, without need of an input PLL for synchronisation. The audio samples are output serially in I2S format. PLL interface to filter out the jitter and generate a jitter-free I2S output. Recognizes all common audio and video related sample frequencies and outputs a nibble code for each.
5.3.9.1 SPDIF register description
Table 34 SPDIF status register Name I2SIN_SPDIF_STATUS Base AS3525_I2SIN_BASE Default 0x00
Offset: 0x0018
SPDIF status signals register This read-only register contains status information of the SPDIF interface. The spdif_sample_freq and spdif_sync status bits are directly derived from the SPDIF converter. In order to provide valid status bits, these signals must be synchronized with pclk, i.e. clk_i2sin. Default Access R R Bit Description Incoming sample frequency Recognition of sub-frame preamble 0: first sub-frame preamble not recognized 1: successful recognition of the first sub-frame preamble
Bit 4:1 0
Bit Name spdif_sample_freq spdif_sync
The following table shows the input sample rate in KHz according to the sample_freq_code (bit 5 to 1) in the I2SIN_SPDIF register. sample_freq_code 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Input Sample Rate (KHz) 22.050 24.000 32.000 44.100 48.000 64.000 88.200 96.000 176.400 192.000
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5.3.10 I2SOUT - I2S output interface
The I2S output interface module (called I2SOUTIF module hereafter) is used to connect the processor system to an audio DAC. The communication is based on the standardized I2S interface. The audio samples are transferred from the processor to the I2SOUTIF module using the AMBA APB bus. A FIFO for 128 dual-channel audio samples is provided as a data buffer. Furthermore, the module provides a set of data, control and status registers. The I2SOUTIF provides the following features: * * * * * * * two independent clock domains: AMBA APB clock PCLK, I2S output clock i2so_mclk FIFO (128 words with 36 bit) separating clock domains support of 16 and 18 bit audio samples clock generator for I2S clocks (LCLK, I2SO_SCLK) support of several oversampling rates: 128x, 256x, 512x interrupt support for FIFO data write DMA support for FIFO data transfer
For data output, following modes are implemented: * * * * two 18 bit audio samples, one for each channel (R,L). The values are written to I2SO_DATA. two 16 bit audio samples, one for each channel (R,L). Both values are written to the 32-bit wide I2SO_DATA register at the same time. This mode is highly efficient for 32-bit processor architectures. one 18 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SO_DATA. one 16 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SO_DATA.
Figure 26 I2SO Block Diagram
5.3.10.1 I2S Output Interface Registers
Table 35 I2S Output Interface Registers Base Address AS3525_I2SOUT_BASE AS3525_I2SOUT_BASE AS3525_I2SOUT_BASE AS3525_I2SOUT_BASE AS3525_I2SOUT_BASE AS3525_I2SOUT_BASE Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 Control register Interrupt mask register Raw status register Status register Interrupt clear register Audio data register Note
Register Name I2SOUT_CONTROL I2SOUT_MASK I2SOUT_RAW_STATUS I2SOUT_STATUS I2SOUT_CLEAR I2SOUT_DATA
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AS3524 C21 / C22 Data Sheet, Confidential Table 36 I2SOUT control register Name I2SOUT_CONTROL Offset: 0x0000 Bit 6 Bit Name DMA_req_en Base AS3525_I2SOUT_BASE
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Default 0x0C
Control register 7 bit wide read/write register containing the control bits of the I2SOUTIF. Default 0 Access R/W Bit Description DMA request enable 0: disable 1: enable I2SDATA loopback from I2SINIF 0: I2SOUT_SDATA source is I2SOUTIF's FIFO 1: I2SOUT_SDATA source is loopback value from I2SINIF (signal I2SIN_FDATA) Invert MCLK 0: disable (SCLK changes at MCLK's falling edge) 1: enable (SCLK changes at MCLK's rising edge) Audio samples provided by processor 0: mono 1: stereo Bit width of audio samples provided by processor 0: 16 bit 1: 18 bit Oversampling rate 00: 128x 01: 256x 10: 512x 11: 128x
5
sdata_lb
0
R/W
4
mclk_invert
0
R/W
3
stereo_mode
1
R/W
2
18bit_mode
1
R/W
1,0
osr
00
R/W
CAUTION: The control bit sdata_lb can only be set, if the I2SIN_FSDATA is synchronous to I2SOUT_SCLK. This is the case if AFE is used together with the AS3525 (in this case the I2SINIF uses also I2SOUT_CLK). Table 37 I2S Output mask register Name I2SOUT_MASK Offset: 0x0004 Bit 7 6 5 4 3 2 1 0 Bit Name reserved I2SOUT_MASK_POER I2SOUT_MASK_PUE I2SOUT_MASK_PUAE I2SOUT_MASK_PUHF I2SOUT_MASK_PUAF I2SOUT_MASK_PUF I2SOUT_MASK_PUER Base AS3525_I2SOUT_BASE Default 0x00
Interrupt mask register The interrupt mask register determines which status flags generate an interrupt by setting the corresponding bit to 1. Default 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit Description stereo18_status cannot assert interrupt request 1 enables the FIFO POP error interrupt 1 enables the FIFO PUSH is empty interrupt 1 enables the FIFO PUSH is almost empty interrupt 1 enables the FIFO PUSH is half full interrupt 1 enables the FIFO PUSH is almost full interrupt 1 enables the FIFO PUSH is full interrupt 1 enables the FIFO PUSH error interrupt
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AS3524 C21 / C22 Data Sheet, Confidential Table 38 I2S output raw status register Name I2SOUT_RAW_STATUS Base AS3525_I2SOUT_BASE
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Default 0x00
Offset: 0x0008
Raw status register The read-only raw status register contains the actual bit values as reflected by the FIFO controller status signals. I2SOUT_POER and I2SOUT_PUER are static bits, since FIFO controller gives the PUSH/POP error bit only for one clock. This means that these two bits remain asserted until they are cleared in the I2SOUT_CLEAR register. All other bits change state depending on the underlying logic, i.e. state of FIFO controller. Default 0 Access R Bit Description Status of write interface for 18 bit stereo mode 0: left audio sample is expected next 1: right audio sample is expected next 1 if FIFO POP error 1 if FIFO PUSH is empty 1 if FIFO PUSH is almost empty 1 if FIFO PUSH is half full 1 if FIFO PUSH is almost full 1 if FIFO PUSH is full 1 if FIFO PUSH error
Bit 7
Bit Name stereo18_status
6 5 4 3 2 1 0
I2SOUT_POER I2SOUT_PUE I2SOUT_PUAE I2SOUT_PUHF I2SOUT_PUAF I2SOUT_PUF I2SOUT_PUER
0 0 0 0 0 0 0
R R R R R R R
Table 39 I2S output status register Name I2SOUT_STATUS Base AS3525_I2SOUT_BASE Default 0x00
Offset: 0x000C
Status register The status register is a read-only register. A read to this register returns the value of the raw status bits AND'ed with the corresponding mask of enable bits set in the mask register. Default 0 Access R Bit Description Status of write interface for 18 bit stereo mode 0: left audio sample is expected next 1: right audio sample is expected next 1 if FIFO POP error 1 if FIFO PUSH is empty 1 if FIFO PUSH is almost empty 1 if FIFO PUSH is half full 1 if FIFO PUSH is almost full 1 if FIFO PUSH is full 1 if FIFO PUSH error
Bit 7
Bit Name stereo18_status
6 5 4 3 2 1 0
I2SOUT_POER I2SOUT_PUE I2SOUT_PUAE I2SOUT_PUHF I2SOUT_PUAF I2SOUT_PUF I2SOUT_PUER
0 0 0 0 0 0 0
R R R R R R R
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AS3524 C21 / C22 Data Sheet, Confidential Table 40 I2S output interrupt clear register Name I2SOUT_CLEAR Base AS3525_I2SOUT_BASE
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Default 0x00
Offset: 0x0010
Interrupt clear register The interrupt clear register is a write-only register. The corresponding static status bit can be cleared by writing a 1 to the corresponding bit in the clear register. All other interrupt flags are level interrupts depending on the status of the FIFO. The bits are de-asserted depending on the FIFO controller. Default Access W W W W Bit Description Clear POP error interrupt flag Clear PUSH error interrupt flag
Bit 7 6 5:1 0
Bit Name reserved I2SOUT_clear_poer reserved I2SOUT_clear_puer
I2SOUT_DATA
The I2SOUTIF provides two 32 bit wide data registers. The registers are used to store the audio samples before they are written to the FIFO. The registers can be used in different modes depending on the setting of the I2SOUT_CONTROL register. Basically, there are four ways to fill the FIFO. The processor can provide * * * * two 18 bit audio samples, one for each channel (R,L). The values are written to I2SOUT_DATA. two 16 bit audio samples, one for each channel (R,L). Both values are written to the 32-bit wide I2SOUT_DATA register at the same time. This mode is highly efficient for 32-bit processor architectures. one 18 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SOUT_DATA. one 16 bit mono audio sample; the sample is used for both channels (R and L). The value is written to the I2SOUT_DATA.
In 18 bit stereo mode the data in I2SOUT_DATA is interpreted either as left or right audio value. The stereo18_status bit in the I2SOUT_STATUS register provides the information which channel's audio sample is expected next.
The I2S Output Signals
The following specifications signals are given: * * Data are valid at the rising edge of I2SO_SCLK. The MSB is left justified to the I2S frame identification (I2SO_LRCK). According to standard I2S definition, a delay of one clock cycle between transition of I2SO_LRCK and the data MSB is used.
The timing diagram of the I2S interface signals for 18bit and 16bit DAC is shown below.
Tperiod(fsaudio) / 2 Tperiod(fsaudio) / 2
I2SO_MCLK I2SO_LRCK I2SO_SCLK I2SO_SDATA
16 bit Left Channel Right Channel
15
2
1
0
15
2
1
0
I2SO_SDATA
18 bit
17
2
1
0
17
2
1
0
Figure 27 - I2S output timing diagram
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AS3524 C21 / C22 Data Sheet, Confidential For the relationship of the clocks following constraints must be met: * *
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LRCK must change with the falling edge of MCLK while MCLK is low (constrained should be set to 40 % of the MCLK period, see figure below). SDATA must change at the falling edge of SCLK. It will be read with the rising edge of SCLK.
Figure 28 Clock constraints
I2SO_MCLK Lrck must change with falling edge, within 40 % of MCLK period
I2SO_LRCK
I2SO_SCLK Sampling of I2S data by Cello IF with rising edge of SCLK I2SO_SDATA L15 L14 R15 R14
5.3.10.2 Power Modes
The I2SOUTIF contains two clock domains. Each clock domain can be turned off separately. The I2SO_MCLK must be turned off in the global clock controller register. This is necessary, as the audio chip requires I2SO_MCLK and I2SO_SCLK not only for I2S output, but also I2S input (see I2SINIF).
PCLK Idle Mode
If the PCLK is turned off (by the clock controller) the I2SOUT_STATUS register can hold invalid data. However, no interrupt should be triggered if the I2SOUTIF is in idle mode.
I2SO_MCLK Idle Mode
If I2SO_MCLK is disabled (by the clock controller) no audio samples are read from the FIFO. The output signals remain unchanged until the I2SO_MCLK is enabled again.
5.3.10.3 Loopback Feature
On the AS3525 are two I2S interfaces: * * I2SOUTIF is responsible to send values to the DAC of the audio chip via I2SO_SDATA I2SINIF is responsible to receive audio values from ADC of the audio chip via I2SI_SDATA
In the AS3525 both SDATA signals are provided as loopback signals (I2SO_FSDATA, I2SI_FSDATA): * * I2SO_SDATA to I2SINIF: This loopback is mainly for testing the transmission and reception paths of both I2S interfaces. The loopback signal is called I2SO_FSDATA. I2SI_SDATA to I2SOUTIF: This loopback feature allows the application to echo the input audio samples directly to a loudspeaker. The signal provided by the I2SINIF is called I2SI_FSDATA.
In normal mode the I2SOUTIF generates the I2SO_SDATA signal based on the contents of the FIFO. If the loop back feature is enabled, the SDATA_LB bit in the I2SOUT_CONTROL register must be set. NOTE: This feature will only be available if SCLK is the same for I2S input and output interface. For implementation the I2SI_FSDATA signal is simply routed through a multiplexer to the I2SO_SDATA interface.
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AS3524 C21 / C22 Data Sheet, Confidential
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5.3.10.4 DMA Interface
The I2SOUTIF supports DMA transfers. The DMA controller supports incrementing and non-incrementing (single address) addressing for source and destination. For I2SOUTIF the single-address mode is used. The address of the I2SOUT_DATA register is used as DMA destination address.
Stereo 18 bit DMA Mode
In 18 bit stereo mode, right and left audio samples must be transferred separately to the FIFO. In single-address DMA-mode both data must be written to the same address. The I2SOUTIF is responsible to put the two 18 bit samples together to a 36 bit word. This word is written into the 36 bit wide FIFO. The I2SOUTIF requires a specific ordering of the samples written to the I2SOUT_DATA register: first the left value must be written, and afterwards the DMA controller must write the right value. Then a left value can follow, a.s.o. The status bit stereo18_status shows which audio sample is expected. In order to set up a correct DMA transfer the values must be placed in the source memory as follows: Address addr 0 addr 1 addr 2 addr 3 ... addr n*2 addr n*2+1 LDATA 0 RDATA 0 LDATA 1 RDATA 1 ... LDATA n RDATA n Value
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AS3524 C21 / C22 Data Sheet, Confidential
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5.3.11 NAND Flash Interface
The NAND FLASH interface module enables control of NAND flash devices. The design follows the hardware reference implementation described in SMIL (SmartMediaTM Interface Library), Hardware Edition 1.00, TOSHIBA Corporation, but has extensions to support the latest generation of NAND flash devices. Programming and Reading can be done either by direct access to/from data register (normal mode) or by using a FIFO (burst mode). NAF supports 8-bit and 16-bit transfers.
Features
* * * * * * * * * * * * * * * interface compliant to AMBA APB bus generation of interrupt request signal with several maskable interrupt sources (ready, empty, almost_empty...) hardware error detection (2 detect, 1 correct per 256 bytes block) for up to 8 *256 bytes (up to 24 ECC bytes) 8-bit and 16-bit transfer Mode fore X8/X16 devices big endian / little endian support DMA Mode Normal Mode Data/Mode/Status Register write/read on/from data register automatically generates read/write strobes Burst Transfer 36 x 32 bit FIFO for DMA/burst support read- & write controller for automatic data resizing (32bit <=> 8/16bit) and read/write control configurable strobe (low and high time) for higher PCLK clocks / lower speed NAND Flash devices little endian/ big endian selectable load interrupts when FIFO is `almost_empty' & 'almost_full' to ensure continuous data flow
Figure 29 Block Diagram of NAND Flash Interface
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AS3524 C21 / C22 Data Sheet, Confidential Figure 30 Connecting a NAND Flash
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5.3.11.1 NandFlash Interface Registers
Table 41 NAF registers Register Name NAFCONFIG NAFCONTROL NAFECC NAFDATA NAFMODE NAFSTATUS NAFMASK NAFFIFODATA NAFWORDS NAFCLEAR NAFTEST Base Address AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE AS3525_NAND_FLASH_BASE Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 Configuration register Control register Error correction code reg Data register Mode register Status register Interrupt mask register buffered read/write data register Words register Interrupt clear register Test register Note
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AS3524 C21 / C22 Data Sheet, Confidential Table 42 NAF configuration register Name NAFConfig Base AS3525_NAND_FLASH_BASE
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Default 0x00
Offset 0x0000
NAF Configuration Register The register is used for basic setup. 8 or 16-bit data width, little or big endian can be selected. DMA and FIFO on/off can be controlled as well as duty cycle and duration of read & write signals. Default 0x00 Access R/W Bit Description low time (# of PCLK cycles + 1) of the output `naf_we_n' (e.g. a value of 1 will keep naf_we_n at `0' for 3 PCLK cycles during write) high time (# of PCLK cycles + 2) of the output `naf_we_n' (e.g. a value of 0 will keep naf_we_n at `1' for 2 PCLK cycles during write) low time (# of PCLK cycles + 1) of the output `naf_re_n' (e.g. a value of 2 will keep naf_re_n at `0' for 3 PCLK cycles during read) high time (# of PCLK cycles + 2) of the output `naf_re_n' (e.g. a value of 0 will keep naf_re_n at `1' for 2 PCLK cycles during read) 0: DMA is disabled and all DMA request signals are tied to 1: DMA is enabled 0: FIFO is reset 1: FIFO is enabled 0: little endian (FIFO data word will be processed in the order word(7:0), word(15:8), word(23:16) and word(31:24) when x16_device is 0; word(15:0) and word(31:16) when x16_device is 1 1: big endian (FIFO data word will be processed in the order word(31:24), word(23:16), word(15:8) and word(7:0) when x16_device is 0; word(31:16) and word(15:0) when x16_device is 1 Note: big_endian is only supported for r/w access through register NAFFifodata 0: X8 Device (for NAND flash with 8-bit data bus) 1: X16 Device (for NAND flash with 16-bit data bus)
Bit 19:16
Bit Name write_strobe_low [3:0]
15:12
write_strobe_high [3:0]
0x00
R/W
11:8
read_strobe_low [3:0]
0x00
R/W
7:4
read_strobe_high [3:0]
0x00
R/W
3
dma_on
0x0
R/W
2
fifo_staticreset_n
0x0
R/W
1
big_endian
0x0
R/W
0
x16_device
0x0
R/W
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AS3524 C21 / C22 Data Sheet, Confidential Table 43 NAF control register Name NAFControl Offset 0x0004 Bit 1 Bit Name read_strobe Base AS3525_NAND_FLASH_BASE NAFControl Register
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Default 0x2
The NAFControl register controls read access and FIFO dynamic reset. Default 0x1 Access W Bit Description 1: triggers a FIFO reset pulse (when NAFConfig bit `fifo_staticreset_n' is 1) The bit is cleared automatically in the next PCLK cycle. 1: triggers one single read cycle on output `naf_re_n'. The bit is cleared automatically in the next PCLK cycle.
0
fifo_reset_strobe
0x1
W
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AS3524 C21 / C22 Data Sheet, Confidential Table 44 NAF error correction register Name NAFEcc Offset 0x0008 Bit Bit Name Base AS3525_NAND_FLASH_BASE
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Default 0x2
NAF Error correction code register The NAFEcc register offers access to the error correction code registers. Default Access Bit Description This register can be accessed up to 8 times and contains the following data: 1.access => Line Parity Block1 2.access => Column Parity Block1** 3.access => Line Parity Block2 4.access => Column Parity Block2** 5.access => Line Parity Block3 6.access => Column Parity Block3** 7.access => Line Parity Block4 8.access => Column Parity Block4** (9.access => same as 1.access)
32:0
Nafecc [32:0]
0x0001
R
Note: * Before access to NAFEcc registers is possible, NAFMode register has to be set to 0xd4 (after page write operation) or to 0x54 (after page read operation). NAFEcc register contents will be cleared if NAFMode register bits 6 and 5 are both `1'. ** Only bits 11 to 0 are relevant for column parity, other bits are `0'; The content of NAFEcc depends on the device type. X8 (8-bit data bus) devices: Line Parity Block1 : will contain the line Column Parity Block1 : will contain the column Line Parity Block2 : will contain the line Column Parity Block2 : will contain the column Line Parity Block3 : will contain the line Column Parity Block3 : will contain the column Line Parity Block4 : will contain the line Column Parity Block4 : will contain the column X16 (16-bit data bus) devices: Line Parity Block1 : will contain the line Column Parity Block1 : will contain the column Line Parity Block2 : will contain the line Column Parity Block2 : will contain the column Line Parity Block3 : will contain the line Column Parity Block3 : will contain the column Line Parity Block4 : will contain the line Column Parity Block4 : will contain the column
parity of byte 1 to 512 (after 512 r/w cycles) parity of byte 1 to 512 (after 512 r/w cycles) parity of byte 513 to 1024 (after 1024 r/w cycles) parity of byte 513 to 1024 (after 1024 r/w cycles) parity of byte 1025 to 1536 (after 1536 r/w cycles) parity of byte 1025 to 1536 (after 1536 r/w cycles) parity of byte 1537 to 2048 (after 2048 r/w cycles) parity of byte 1537 to 2048 (after 2048 r/w cycles)
parity of halfword(7:0) 1 to 512 (after 512 r/w cycles) parity of halfword(7:0) 1 to 512 (after 512 r/w cycles) parity of halfword(15:8) 1 to 512 (after 512 r/w cycles) parity of halfword(15:8) 1 to 512 (after 512 r/w cycles) parity of halfword(7:0) 513 to 1024 (after 1024 r/w cycles) parity of halfword(7:0) 513 to 1024 (after 1024 r/w cycles) parity of halfword(15:8) 513 to 1024 (after 1024 r/w cycles) parity of halfword(15:8) 513 to 1024 (after 1024 r/w cycles)
Note: Read ECC is not performed in unbuffered READ mode (this means when CPU accesses the Nand Flash through the NAF_DATA registers)
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AS3524 C21 / C22 Data Sheet, Confidential Table 45 NAF data register Name NAFData Offset 0x000C Bit 15:0 Bit Name NAFData Base AS3525_NAND_FLASH_BASE
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Default 0x0000
Data Register The NAFData register offers unbuffered access to the data bus of the NAND flash device. Default 0x01 Access R/W Bit Description For X8 devices (8-bit data bus) only bits 7:0 are relevant, other bits are ignored For X16 devices (16-bit data bus) all are relevant
Table 46 NAF mode register Name NAFMode Offset 0x0010 Bit 7 Bit Name write protection Base AS3525_NAND_FLASH_BASE Mode register The NAFMode register controls NAND flash read/write/erase procedures. Default 0x0 Access R/W Bit Description Used to control `command latch enable' 0: output `naf_cle' is set to `0' 1: output `naf_cle' is set to `1' (Command Latch Cycle) controls `address latch enable' 0: output `naf_ale' is set to `0' 1: output `naf_ale' is set to `1' (Address Latch Cycle) 0: power off (all output enable signals are turned off) 1: power on Default 0x00
6:5
Ecc [1:0]
0x0
R/W
4
ce
0x0
R/W
3
-
0x0
R/W
always `0'
2
power_on
0x0
R/W
0: power off (all output enable signals are turned off) 1: power on controls `address latch enable' 0: output `naf_ale' is set to `0' 1: output `naf_ale' is set to `1' (Address Latch Cycle) controls `command latch enable' 0: output `naf_cle' is set to `0' 1: output `naf_cle' is set to `1' (Command Latch Cycle)
1
ale
0x0
R/W
0
Cle
0x0
R/W
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AS3524 C21 / C22 Data Sheet, Confidential Table 47 NAF status register Name NAFStatus Offset 0x0014 Bit Bit Name Base AS3525_NAND_FLASH_BASE Status Register
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Default -
The NAFStatus register contains information on the internal status. Defau lt Access Bit Description FIFO error signal 0: if FIFO is reset 1: if FIFO contains 36 words and FIFO push(write) has occurred or when FIFO contains 0 words and a FIFO pop(read) has occurred. The FIFO error will lock the FIFO and has to be reset by a reset of the FIFO (by setting NAFControl register bit 1 to `1') FIFO full signal 0: if FIFO contains less than 36 words 1: if FIFO contains 36 words FIFO almost_full signal 0: if FIFO contains less than 32 words 1: if FIFO contains more than or equal 32 words FIFO almost_empty signal 0: if FIFO contains more than 4 words 1: if FIFO contains less than or equal 4 words FIFO empty signal 0: if FIFO contains more than 0 words 1: = when FIFO contains 0 words read/write strobe ready signal 0: if read/write strobe `0' (strobe active) 1: if read/write strobe `1' (strobe inactive) synchronised NAND flash ready signal 0: if synchronised input `naf_busy_in_n' is `0' (busy) 1: if synchronised input `naf_busy_in_n' is `1' (ready) FIFO error indication (edge triggered) 0: if bit 6 of NAFClear register is set to `1' 1: if FIFO contains 36 words and FIFO push(write) occurs or when FIFO contains 0 words and a FIFO pop(read) occurs. FIFO full indication (edge triggered) 0: if bit 5 of NAFClear register is set to `1' 1: if FIFO contains 36. FIFO high indication (edge triggered) 0: if bit 4 of NAFClear register is set to `1' 1: if FIFO gets full (36 words) or changes from 31 to 32 words (and when the NAFWords register is greater than 32). Note: When this bit gets `1' during `Page Read' mode, a new FIFO burst read of up to 32 words is possible. FIFO low indication (edge triggered) 0: if bit 3 of NAFClear register is set to `1' 1: if FIFO gets empty or changes from 5 to 4 words (and when the NAND Flash requires more than 32 bytes/halfwords). Note: When this bit gets `1' during `Page Programming' mode, a new FIFO burst write of up to 32 words is possible
13
fifo_error
0x0
R
12
fifo_full
0x0
R
11
fifo_almost_full
0x0
R
10
fifo_almost_empty
0x0
R
9
fifo_empty
0x0
R
8
strobe_ready
0x0
R
7
flash_ready
0x0
R
6
got_fifo_error
0x0
R
5
got_fifo_full
0x0
R
4
got_fifo_high
0x0
R
3
got_fifo_low
0x0
R
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AS3524 C21 / C22 Data Sheet, Confidential Name NAFStatus Offset 0x0014 Bit Bit Name Base AS3525_NAND_FLASH_BASE Status Register
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Default -
The NAFStatus register contains information on the internal status. Defau lt Access Bit Description NAFWords empty and Controller ready indication (edge triggered) 0: when bit 2 of NAFClear register is set to `1' 1: when read/write strobe changes from `0' to `1' (end of strobe) and NAFWords register has become empty. Note: This bit is used to detect the end of a multiple read/write burst transaction Read/write strobe ready indication (edge triggered) 0: when bit 1 of NAFClear register is set to `1' 1: when read/write strobe changes from `0' to `1' (end of strobe) Note: read/write strobes can last from 3 to 33 PCLK cycles depending on NAFConfig settings. NAFWords empty and Controller ready indication (edge triggered) 0: when bit 2 of NAFClear register is set to `1' 1: when read/write strobe changes from `0' to `1' (end of strobe) and NAFWords register has become empty. Note: This bit is used to detect the end of a multiple read/write burst transaction
2
got_empty_and_rdy
0x0
R
1
got_strobe_ready
0x0
R
0
got_flash_ready
0x0
R
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AS3524 C21 / C22 Data Sheet, Confidential Table 48 NAF interrupt mask register Name NAFMask Offset 0x0018 Bit 6 Bit Name mask6 Base AS3525_NAND_FLASH_BASE Interrupt Mask Register
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Default 0x0018
The NAFMask register is used to mask/enable the internal interrupt requests. Default 0x1 Access R/W Bit Description Mask `FIFO error indication' interrupt request 0: enable 1: masked Mask `FIFO full indication' interrupt request 0: enable 1: masked Mask `FIFO high indication' interrupt request 0: enable 1: masked Mask `FIFO low indication' interrupt request 0: enable 1: masked Mask `NAFWords empty and Controller ready indication' interrupt request 0: enable 1: masked Mask `Read/write strobe ready indication' interrupt request 0: enable 1: masked Mask `NAND flash ready indication' interrupt request 0: enable 1: masked
5
mask5
0x1
R/W
4
mask4
0x1
R/W
3
mask3
0x1
R/W
2
mask2
0x1
R/W
1
mask1
0x1
R/W
0
mask0
0x1
R/W
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AS3524 C21 / C22 Data Sheet, Confidential Table 49 NAF FiFo Data register Name NAFFifodata Offset 0x001c Bit Bit Name Base AS3525_NAND_FLASH_BASE FIFO Data Register
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Default 0x0000
The NAFFifodata register offers access to the internal FIFO. Default Access Bit Description Writing this register will push a word on the FIFO and the write address will be incremented by 1. When the FIFO is full (36 words) then a write access on the register is ignored and the FIFO ERROR status bit is set. Reading on this register will pop a word from the FIFO and the read address will be incremented by 1. When the FIFO is empty then a read access on the register is ignored and the FIFO ERROR status bit is set.
32:0
Fifodata [32:0]
-
R/W
Table 50 NAF interrupt mask register Name NAFWords Offset 0x0020 Bit 32:0 Bit Name Words [32:0] Base AS3525_NAND_FLASH_BASE Default 0x0000
Interrupt Mask Register The NAFWords register informs the controller about the maximum words to be transferred and controls the FIFO transfer both in interrupt and DMA mode. Default 0x0000 Access R/W Bit Description 0: FIFO based data transfer is disabled not 0: FIFO transfer is in progress
Note: For page transfers (program or read) the initial number of words depends on the NAND flash device. For a page size of 512 bytes, an initial word value of 512/4 = 128 has to be written. For a page size of 2k bytes, an initial word value of 512 has to be used.
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AS3524 C21 / C22 Data Sheet, Confidential Table 51 NAF interrupt clear register Name NAFClear Offset 0x0024 Bit 6 Bit Name clear6 Base AS3525_NAND_FLASH_BASE
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Default 0x0018
Clear Register The NAFClear register clears interrupt status information and re-enables interrupt detection. Default Access W Bit Description Reset of `FIFO error indication' status bit 0: no action 1: bit 6 of NAFStatus is reset and interrupt 6 detection is enabled Reset of `FIFO full indication' status bit 0: no action 1: bit 5 of NAFStatus is reset and interrupt 5 detection is enabled Reset of `FIFO high indication' status bit 0: no action 1: bit 4 of NAFStatus is reset and interrupt 4 detection is enabled Reset of `FIFO low indication' status bit 0:no action 1:bit 3 of NAFStatus is reset and interrupt 3 detection is enabled Reset of `NAFWords empty and Controller ready indication' status bit 0:no action 1:bit 2 of NAFStatus is reset and interrupt 2 detection is enabled Reset of `Read/write strobe ready indication' status bit 0: no action 1: bit 1 of NAFStatus is reset and interrupt 1 detection is enabled Reset of `Read/write strobe ready indication' status bit 0:no action 1: bit 0 of NAFStatus is reset and interrupt 0 detection is enabled
5
clear5
-
W
4
clear4
-
W
3
clear3
-
W
2
clear2
-
W
1
clear1
-
W
0
clear0
-
W
Table 52
NAF test register Name NAFTest Base AS3525_NAND_FLASH_BASE Test Register The NAFTest register is used for functional tests of the FIFO. Default Access W Bit Description 0: default mode 1: disables FIFO access by the internal controller => FIFO is accessed by APB interface only 0: default mode 1: data word both on FIFO input and output is inverted Default 0x0000
Offset 0x0028 Bit 1 Bit Name datainvert
0
fifotest
-
W
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AS3524 C21 / C22 Data Sheet, Confidential
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5.3.12 DBOP - Data Block Output Port
Purpose of this ARM APB peripheral module is a high-speed data output port that can support data transfer to various display controllers based on synchronous control interfaces. Programmability of polarity and timing of the generated control signals makes it possible to support various kinds of displays. Example of a supported display controller is the Hitachi HD77766R LCDE controller. From the programmers point of view the DBOP module can be serviced by DMA accesses. With the large size of the data FIFO and the programmable interrupt request conditions the overhead for SW is minimised. Simple read instructions to read for example a status register of the LCD controller are also supported. The usage of this cell results in a great performance boost compared to the standard ARM GPIO PrimeCellTM architecture.
Features
* * * * * * * * * * * APB bus interface support for direct memory access (DMA) data output FIFO with 128 words (32 bit wide) 8 or 16 bit parallel data output (configurable) 4 control outputs - flexible programming of the signal waveforms with respect to polarity and timing programmable even/odd control output generation 8 or 16 bit parallel data input register with programmable read strobe programmable conditions for interrupt generation based on FIFO flags usage of FIFO for simple division of APB clock domain and output clock domain programmable data output rate in range of 0.05 to 4 MHz APB Clock & DBOP Clocks are synchronous.
Figure 31 DBOP Block Diagram
DBOP
FiFo 128x32 Dual ported RAM 128x32
PRESETn PSEL PENABLE PWRITE PADDR[11:2] PWDATA[31:0] PRDATA[7:0] PCLK 32 32
Amba APB Interface
Dout register
lb_select, hb_select
dbop_d[7:0] / xpc[7:0] dbop_d[11:8] / xpb[7:4]
push FiFo push status
pop
symetric FiFo Controller
dbop_d[15:12]
FiFo pop status
c0 / xpb[0]
Control Signal Generator
c1 / xpb[1] c2 / xpb[2] c3 / xpb[3]
Register Block
dinStrobe dataValid 8
Din register
din[7:0]
DBOPDMASREQ DBOPDMABREQ DBOPDMACLR
DMA Interface
Interrupt Generator
DBOPIRQ
dbop_clk
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5.3.12.1 DBOP register definitions
Table 53 DBOP Registers Register Name DBOP_TIMPOL_01 DBOP_TIMPOL_23 DBOP_CTRL_REG DBOP_STAT_REG DBOP_DOUT_REG DBOP_DIN_REG Base Address AS3525_DBOP_BASE AS3525_DBOP_BASE AS3525_DBOP_BASE AS3525_DBOP_BASE AS3525_DBOP_BASE AS3525_DBOP_BASE Offset 0x00 0x04 0x08 0x0C 0x10 0x14 Note Timing and polarity for control 0 and 1 Timing and polarity for control 1 and 2 Control Register Status Register Data output register Data input register
Timing & Polarity Control register TPC01
This register contains all information necessary for definition of control signals C0 and C1. Table 54 DBOP control registers C0 and C1 Register bits 31 30 29 28:24 23:19 18 17 16 15 14 13 12:8 7:3 2 1 0 Name c1_p0 c1_p1 c1_p2 c1_t1 c1_t2 c1_ev c1_od c1_qs c0_p0 c0_p1 c0_p2 c0_t1 c0_t2 c0_ev c0_od c0_qs type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function polarity 1 polarity 2 polarity 3 Time 1 Time 2 even enable odd enable quiescent state polarity 1 polarity 2 polarity 3 Time 1 Time 2 even enable odd enable quiescent state default value 0 1 0 0xA 0x14 1 1 0 0 1 0 0xA 0x14 1 1 0
Timing & Polarity Control register TPC23
This register contains all information necessary for definition of control signals C2 and C3. Table 55 DBOP control registers C2 and C3 Register bits 31 30 29 28:24 23:19 18 17 16 15 14 13 12:8 7:3 2 1 0 Name c3_p0 c3_p1 c3_p2 c3_t1 c3_t2 c3_ev c3_od c3_qs c2_p0 c2_p1 c2_p2 c2_t1 c2_t2 c2_ev c2_od c2_qs type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w function polarity 1 polarity 2 polarity 3 Time 1 Time 2 even enable odd enable quiescent state polarity 1 polarity 2 polarity 3 Time 1 Time 2 even enable odd enable quiescent state default value 0 1 0 0xA 0x14 1 1 0 0 1 0 0xA 0x14 1 1 0
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Table 56 DBOP control register Register bits 31:22 21 20 Name type function reserved Interrupt clear signal for pop error interrupt Interrupt clear signal for push error interrupt Tri-state enable for dout bus short count bit reset to even cycle enable write start read output serial mode default value 0 0 Writing 1 to this bit will clear the pop error interrupt. Writing 0 has no effect. Writing 1 to this bit will clear the push error interrupt. Writing 0 has no effect . When set, dout bus is tri-stated when there is no active write on the bus. when set, next output cycle is even 0: write disabled 1: write enabled 0: 1: 2: 0: 1: 0: 1: single word out 2 serial words out 4 serial words out 8 bit data width 16 bit data width all IR disabled IR enabled
clr_pop_err clr_push_err
W W
19 18 17 16 15 14:13
en_data sdc res_even enw strd osm
r/w r/w r/w r/w r/w r/w
0 0 0 0 0 0
12 11 10 9 8 7 6 5 4:0
ow ir_enable ir_po_err ir_pu_err ir_e_en ir_ae_en ir_af_en ir_f_en rs_t
r/w r/w r/w r/w r/w r/w r/w r/w r/w
output data width IR enable IR enable on pop error IR enable on push error IR enable set on push empty IR enable set on push almost empty IR enabbe set on push almost full IR enable set on push full read strobe time
0
0 0 0 0 0 0 0x1F
Notes: If the start read bit is issued by setting the strd bit to 1, a single read cycle is generated. After this read cycle the strd bit is set to 0 again by HW. If write is enabled by setting enw=1, no read is possible (strd does not cause any action). res_even is a reset bit that defines the start of even/odd generated signals. With res_even bit set, the next output cycle is a even cycle. Within this first even output cycle the res_even bit is set to 0 by the SW. sdc selects the counter length for the timing generator. Default is end value of 31. With sdc set to 1, the count end value is 15. en_data is used as a tri-state enable for the dout bus . When set as 1, dout is tri-stated if there is no active write on the bus . When this bit is set as 0, dout is bus is tri-stated only during the read cycle.
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Table 57: DBOP status register Register bits 31:17 16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Name type function reserved read data valid push error push fifo empty push fifo almost empty push fifo half full push fifo almost full push fifo full pop error pop fifo empty pop fifo almost empty pop fifo half full pop fifo almost full pop fifo full default value
rd_d_valid Reserved fi_pu_err fi_pu_e fi_pu_ae fi_pu_hf fi_pu_af fi_pu_f fi_po_err fi_po_e fi_po_ae fi_po_hf fi_po_af fi_po_f
r f r r r r r r r r r r r
The read data valid flag is cleared with every start read and set after read data strobe is issued (at read data valid 1 the data can be readout by SW).
Data Output Register
32 bit register for data output - the data written to this register are directly written to the FiFo. Depending on the serial output mode and the output data width, the effective register width of this register is 8, 16 or 32 bits. Following table shows the effective data width for this register: osm=0 8 (byte0) 16 (HW0) osm=1 16 (byte0, byte1) 32 (HW0, HW1) osm=2 32 (byte0, byte1, byte2, byte3) 32 (HW0, HW1)
odw = 0 odw = 1
Depending on odw, * either one, two or four bytes are transmitted serially for odw=0 * or one or two half words (HW = 16 bits) are transmitted serially for odw=1. Note that for the 8 or 16 bit width only a part of the FiFo memory is used (to keep HW design simple).
Data Input Register
16 bit data input register that holds the value of the last read cycle. It is only valid if the data valid flag is set in the status register. No interrupt support is given, for data input the read data valid flag must be polled.
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Dbop Integration Test Registers
The Dbop module is programmed to integration test mode using test control register. The integration test mode enables the user to access all the input/output pins through the APB bus interface. Name DBOPITC DBOPITIP1 DBOPITOP1 Offset 0x18 0x1C 0x20 R/W R/W R/W R Reset Value 0x00000000 0x00 0x0 Description DBOP integration test control register DBOP integration test input register DBOP integration test output register
Table 58 DBOPITC test register Register bits 31:1 0 Name type function reserved Integration test enable default value 1 will enable the integration test mode
iten
r/w
Table 59 DBOPITIP1 test register Register bits 31:5 4 3 2 1 0 Name type function reserved Test value for out_enControl_n Test value for out_enData_n Test value for DMASREQ Test value for DMABREQ Test value for interrupt default value 0 0 0 0 0 The value on this bit will be reflected in out_enControl_n The value on this bit will be reflected in out_enData_n The value on this bit will be reflected in DBOPDMACSREQ The value on this bit will be reflected in DBOPDMACBREQ The value on this bit will be reflected in DBOPIRQ
Testctrloen Testdataoen Testdmasreq Testdmabreq testirq
r/w r/w r/w r/w r/w
Table 60 DBOPITOP1 test register Register bits 31:1 0 Name type function reserved DBOPDMACCLR test register. default value 0 Read of this register will return the value on the DBOPDMACCLR input.
Testdmaclr
r
5.3.12.2 DBOP DMA Interface
This block generates all necessary interface signals with the DMAC primecell for DMA transfer. Following table gives a description of these signals. DBOPDMASREQ DBOPDMABREQ DBOPDMACLR single word request, asserted by DBOP. This signal is asserted when there is at least one empty location in the FiFo burst DMA transfer request, asserted by DBOP. This signal is asserted when there are at least four empty locations in the FiFo DMA request clear, asserted by DMA controller to clear the DMA request signals. If DMA burst transfer is requested, the clear signal is asserted during the transfer of the last data in the burst
Symmetric FiFo The FiFo buffer has two main purposes: * data buffering: the FiFo contains 128 locations with 32 bits for data storage: with according DMA transfer, the data can be transferred in short time without need for any SW control
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clock domain crossing: the FiFo is at the boarder of clock domain PCLK and DBOPCLK. All necessary synchronisation is done internally. All flags are available as push flags (synchronised to the push clock PCLK) and pop flags (synchronised to the POP clk, which is synchronous to DBOPCLK.
The FiFo controller gives empty, almost empty, half full, almost full and full flags which are available in two fashions: synchronous to the push or the pop side (pop_empty, push_empty, ...).
5.3.12.3 Control Signal Generator
Four independent control signals can be generated: typical application for such signals is a 80xx interface with RS, RD*, WR* and E or a 68xx interface with RS, E, RWN. The idea of this control signal generator is a general-purpose block, which generates any signal timing/waveform that is necessary to transfer the data to any specific display.
Polarity Parameters
For each of the control signals c0 - c3 following polarity parameters are defined: * * * p0 ... polarity 0 at start of cycle p1 ... polarity 1 following polarity 0 p2 ... polarity 2 following polarity 1
Following figure shows an example for timing waveforms defined with these control parameters. Figure 32 DBOP timing waveform
Tperiod
T1 D1 P0, P1, P2 = 000
T2
T1 D2
T2
Static 0
P0, P1, P2 = 001
NRZ 1
P0, P1, P2 = 010 P0, P1, P2 = 011
RZ 1
NRZ 1
P0, P1, P2 = 100 P0, P1, P2 = 101
RZ 1
RO 1
P0, P1, P2 = 110
RZ 1
P0, P1, P2 = 111
Static 1
Quiescent State
The control signals are only generated with each data output cycle (data output cycles are generated as long as the FiFo is not empty). With FiFo empty and in the absence of a read cycle, all control signals are set to a quiescent state. For each control signal, this quiescent state can be programmed either to 1 or 0.
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Timing Parameters
Also the time points for change from p0-p1 (t1) and p1-p2 (t2) can be programmed. For these programmable timing parameters each data output cycle is divided into 32 steps. Both T1 and T2 can be in the range of 0 to 31. For short count bit set (sdc bit in control register), T1 and T2 must be in the range of 0 to 15. Figure 33 DBOP timing parameters
dout Tperiod
D0
0
10
20
30
P0, P1, P2 = 0,1,0; T1=6, T2=10
P0, P1, P2 = 1,0,1; T1=14, T2=28 P0, P1, P2 = 0,0,1; T1<21, T2=21
dinStrobe; TS = 24
Even/odd generated signals In addition to these timing parameters, signals can also be programmed to go active only during the even (0, 2, 4, ...) or the odd cycles (1, 3, 5, ...). For example the indication of even/odd bytes for the case that two bytes in serial are transmitted can be used. Two control bits are used to set this signal behaviour: evenEnable, oddEnable. For default, both are set to 1 and both cycles will appear. For cases where even or odd should be omitted, set according evenEnable/oddEnable to 0. With both set to 0, no cycles will appear at the output! Following example illustrates a typical waveform for an output interface where the evenEnable=0 and oddEnable=1 for control signal C2. In this example, C2 is an active high indication of the high byte (D1, D3, D5, ...). Figure 34 DBOP even/odd generated signals waveforms
quiescent state quiescent state even D0 odd D1 even D2 odd D3 even D4 odd D5
dout
xx
C0 = write C1 = enable
C2 = high byte
C3 = chip select
Normally the even/odd cycles are toggling all the time, also if there are quiescent states in between. To have the possibility of defining a new start, reset of this even/odd counter can be done via the res_even bit inside of the control register. With res_even set, the counter starts with an even cycle. Res_even is then set to 0 again by SW at the new start.
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In addition to the generation of the control signals, also an input strobe signal dinStrobe is generated within the control signal generator. With active dinStrobe, the input data are strobed with rising clock edge (see DIN register).
5.3.12.4 Data Output Register
The data output register handles different output widths and serial output mode (selected by parameters osm and odw). Following diagram illustrates the function of the data output register. Table 61 DBOP data output register
high byte select
Dout[15:7] data output register dout_reg[31:0] D3 D2 D1 D0
Dout[7:0]
low byte select
The control part generates the according signals for low byte select and high byte select.
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5.3.12.5 DIN register
With the dinStrobe, data are written to the DIN register. This gives a simple mechanism, in which for example the status data can be read from a LCD display interface. To do a data read, first the START READ (strd) bit is programmed into the control register. With START READ, the control signal generator starts to generate one cycle with the according control signals. Data are strobed by the programmed strobe time into the din register. After the cycle is completed the HW resets the strd bit to 0. With set of the strd bit, the rd_data_valid bit is also reseted. The SW just has to poll the rd_data_valid bit, when the bit gets set the input data can be read from the din register. After read cycle, the control signal generator returns to the quiescent state. Following timing diagram shows an example of three read cycles. Figure 35 DBOP read cycle example
Read cycle 0
Read cycle 1
Read cycle 2
C0 (= read_n) Data input Read strobe xx D0 D1 D2
DIN register
D0
D1
D2
strd
rd_data_valid
Note: Be aware that the read cycle should only be activated when there is no active write cycle (FiFo is empty). Otherwise the results of such action get unpredictable. For any read cycle, the write enable bit must be set to 0 (write disabled). start read (strd) 0 0 0 0 1 1 1 1 write enable (wen) 0 0 1 1 0 0 1 1 FiFo empty Status 0 1 0 1 0 1 0 1 DBOP function quiescent quiescent valid write quiescent valid read valid read valid write quiescent
5.3.12.6 Interrupt Generator
Depending on the FiFo Status, an interrupt request can be generated. The conditions that cause an interrupt are set within the control register. The interrupt output DBOPIRQ is active high.
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5.3.12.7 Clock frequencies
The input clock is directly taken from the PCLK clock. A programmable prescaler is implemented within the CGU. Input clock for the prescaler is in the range of 20 - 60 MHz. Programmable division factors for the prescaler in the range of 1 to 8. Input clock to the module is in the range of 2.5 to 60 MHz. Within the module the control signal generator is doing a division by 16 or 32 (selectable). So the effective output data rates are in the range of 1.25 to 4 MHz for maximum performance and can be scaled down in the range of 0.07 to 0.25 MHz. Figure 36 DBOP data rate
C0 PCLK (APB clock)
Clock prescaler (inside CGU)
predivider 1 to 8
clk_dbop
Control signal generator
Divider /16 or /32
c1 c2 c3
Output data rate 4.06 MHz 65 MHz ... 20 MHz 65 MHz 8.125 MHz 20 MHz 2.5 MHz
0.25 MHz 1.25 MHz 0.07 MHz
Time constraining for the module should be done with 65 MHz, if there is a demand the time constraints for the output pads can be reduced.
5.3.12.8
Interface with GPIO PINs / additional PINs
For the SW, the usage of either ARM primecell GPIO ports or DBOP port can be configured with the GPIOAFSEL registers.
Following IO ports are used for the basic 8 bit interface
xpc[7:0] xpb[3:0] for dout[7:0] and din[7:0] for {C3, C2, C1, C0}
Following IO ports are used for the optional 16 bit interface
xpb[7:4] dbop_d[15:12] for dout[11:8] and din[11:8] for dout[15:12] and din[15:12]
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5.3.13 UART - Universal Asynchronous Receiver/Transmitter
The UART is a Universal Asynchronous Receiver Transmitter compatible to industry standard 16550 with APB slave interface. This UART provides FIFO based transmitter-receiver pair with programmable Baud-rate, character widths and parity encoding. Status and error information is also provided by the design. Maximum baud rate supported by this UART is 1Mbps for input clock of 16MHz.
Features
* * * * * * * * * Compliance to Industry Standard 16550 UART. APB slave interface. Separate 16x8 Transmit and 16x11 Receive FIFOs. Programmable FIFO disabling for 1-byte depth. Programmable Baud rate Generator. Independent masking for transmit, receive and Error interrupts. False Start bit detection. Line Break generation and detection. Fully programmable serial interface characteristics: Supports 5,6,7 and 8 bits. even, odd, stick and no parity generation and detection. 1, 11/2 and 2 stop bits.
Figure 37 UART Block Diagram
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5.3.13.1 UART Baud Generator and Clock Divider Settings
The internal baud generator module generates the required baud clock using the divisor register value. To achieve correct synchronizationincoming bits are over sampled by a factor of 16x. Software should program the divisor value by which the system clock has to be divided to achieve the required baud clock frequency.
The equation to calculate baud divisor is
Baud Divisor = (input frequency) / (baud rate x 16)
Important: the internal clock divider must be set to a value of 2 or higher. Setting the value to 1 (no division) is not allowed!
For example, for 16 MHz PCLK clock following table gives the list of settings for different BAUD rates. Baud Rate 50 75 110 134.5 150 300 600 1200 1800 2000 4800 7200 9600 19200 38400 56000 128000 250000 300000 500000 Required Baud clock frequency 800 1200 1760 2152 2400 4800 9600 19200 28800 32000 76800 115200 153600 307200 614400 896000 204800 4000000 4800000 8000000 Decimal divisor value 20000 13333 9091 7435 6667 3333 1667 833 556 500 208 139 104 52 26 18 8 4 3 2
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5.3.13.2 UART Register Descriptions
All registers are 8 bits wide. Registers are selected based on the address and the value of Divisor Latch Select (DLS) bit in the line control register (UART_LNCTR_REG). Table 62 UART registers Register Name UART_DATA_REG UART_DLO_REG UART_DHI_REG UART_INTEN_REG UART_INTSTATUS_REG UART_FCTL_REG UART_LNCTL_REG UART_LNSTATUS_REG Table 63 UART Data Register Name UART_DATA_REG Base AS3525_UART_BASE Default 0xC8110000 Base Address AS3525_UART_BASE AS3525_UART_BASE AS3525_UART_BASE AS3525_UART_BASE AS3525_UART_BASE AS3525_UART_BASE AS3525_UART_BASE AS3525_UART_BASE Offset 0x00 0x00 0x04 0x04 0x08 0x0C 0x10 0x14 DLS 0 1 1 0 Note Data register (Rx / Tx) Clock divider lower byte register Clock divider higher byte register Interrupt enable register Interrupt status register FIFO control register Line control register Line status register
Data register Holds the data byte received or the data byte to be transmitted respectively. RX: This register holds the received data byte. In FIFO mode, this byte will be the top byte of the 16-byte FIFO. If FIFO mode is disabled, it will be the content of the receive shift register after a byte has been shifted in. A read to the address value 3b000 with Divisor Latch Select (DLS) bit 1'b0 will give the content of this register. If a character less than 8 bits is received, extra zero bits will be padded to this register. TX: This register contains the data to be transmitted. This register will be written by the processor. In FIFO mode, a write to this address will write data into the FIFO. In FIFO mode, top byte of txFIFO is passed on to transmitter shift register. If FIFO is disabled, a write to the address 3'b000 with DLS bit 1'b0 will write into this register. If FIFO is disabled, this register will be overwritten with new data. If FIFO is disabled, data in this register will be passed on to transmitter shift register. Bit 7:0 Bit Name UART_DATA_REG Default 00000000 Access RW Bit Description Holds the data byte received or the data byte to be transmitted respectively.
Offset: 0x00 DLS bit set to 0
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AS3524 C21 / C22 Data Sheet, Confidential Table 64 UART Clock divider lower byte register Name UART_DLO_REG Base AS3525_UART_BASE
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Default 0xC8110000
Offset: 0x00 DLS set to 1
Clock divider lower byte register This register holds the clock divider value (decimal) which is used to derive the baud clock. To achieve a desired baud rate, the baud clock should be 16-times higher then the baud rate. To derive this clock the ratio of the system clock and the required baud clock should be calculated and the value should be programmed into the clock divider lower byte and higher byte registers (UART_DLO_REG and UART_DHI_REG). Clock divider value = (input frequency) / (baud rate x 16) Default 00000000 Access W Bit Description This register holds the lower byte of the decimal divisor value to calculate baud clock.
Bit 7:0
Bit Name UART_DLO_REG
Table 65 UART Clock divider higher byte register Name UART_DHI_REG Offset: 0x04 DLS set to 1 Bit 7:0 Bit Name UART_DHI_REG Base AS3525_UART_BASE Default 0xC8110000
Clock divider higher byte register This register holds the higher byte of the decimal divisor value to calculate baud clock. Default 00000000 Access W Bit Description This register holds the higher byte of the decimal divisor value to calculate baud clock.
Table 66 UART Interrupt enable register Name UART_INTEN_REG Offset: 0x04 DLS set to 0 Bit 7:3 2 1 0 Bit Name Reserved lnStatusEn txDataEmptyEn rxDataRdyEn Base AS3525_UART_BASE Default 0xC8110000
Interrupt enable register This register will enable the three types of interrupts. Setting the bits of this register to logic 1 enables the selected interrupt. Default 00000 0 0 0 Access W W W Bit Description These bits are reserved for future use. This bit enables the "rxLineStatus" interrupt. This bit enables the "txDataEmpty" interrupt. This bit enables the "rxDataRdy" interrupt.
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AS3524 C21 / C22 Data Sheet, Confidential Table 67 UART Interrupt status register Name UART_INTSTATUS_REG Base AS3525_UART_BASE
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Default 0xC8110000
Offset: 0x08
Interrupt status register This register will give the status of the interrupt. Depending on the enabled interrupt bits in the interrupt enable register (UART_INTEN_REG) different interrupts will be generated and the status will be updated in this register. On sensing an interrupt the software should read this register to get the status of the interrupt. Default 00000 0 Access RU Bit Description These bits are reserved for future use. This interrupt is set on any error condition on the receive line. There are four types of error possibilities. These error conditions are set in bits 4:1 of the line status register (UART_LNSTATUS_REG). This bit is reset on a read of the line status register (UART_LNSTATUS_REG). In FIFO mode this bit is set when txFIFO is empty. If FIFO mode is disabled this interrupt is set if the data register (UART_DATA_REG (Tx)) is empty. This bit will be reset on write to the data register (UART_DATA_REG (Tx)). This is the data ready interrupt. In FIFO mode this bit is set when the number of bytes in the FIFO reaches the trigger level. This bit is also set in FIFO mode when a timeout occurs in the reception, i.e. Rx line idle for more than 4 char times and there is data in the FIFO. If FIFO mode is disabled this bit is set when one full byte is received. This bit is cleared when the FIFO is empty or the data register (UART_DATA_REG (Rx)) is read.
Bit 7:3 2
Bit Name Reserved rxLineStatus
1
txDataEmpty
0
RU
0
rxDataRdy
0
RU
Table 68 UART FIFO control register Name UART_FCTL_REG Offset: 0x0C Bit 7:5 4:3 Bit Name Reserved trigLevel Base AS3525_UART_BASE Default 0xC8110000
FIFO control register This register holds the control parameters to control receive (rx) and transmit (tx) FIFO. The parameters will enable the FIFOs, set the receiver trigger level, etc. Default 000 00 Access W Bit Description These bits are reserved for future use. These two bits will select the trigger level for the rxFIFO. Once the FIFO pointer reaches this level rxDataRdy interrupt is asserted. 00: 01 byte 01: 04 bytes 10: 08 bytes 11: 14 bytes This bit will reset rxFIFO pointers and clear all the bytes in the rxFIFO. This bit is self clearing, i.e. after resetting FIFO this bit will become zero. This bit will reset txFIFO pointers and clear all the bytes in the txFIFO. This bit is self clearing, i.e. after resetting FIFO this bit will become zero. This bit will enable the FIFO mode. By default this will be reset.
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2
rxFIFORst
0
W
1
txFIFORst
0
W
0
FIFOModeEn
0
W
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AS3524 C21 / C22 Data Sheet, Confidential
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Table 69 UART Line control register Name UART_LNCTL_REG Offset: 0x10 Bit 7 Bit Name DLS 0 Base AS3525_UART_BASE Default 0xC8110000
Line control register This register controls the asynchronous data. Parameters in this register set the transmit and receive character format, the data length, parity bit, stop bit length, etc. Default Access RW Bit Description Divisor Latch Select Bit. This bit is used to select Divisor Latch registers. 1: Divisor Latch registers can be accessed. To access other registers this bit should be zero. 1: Will cause a break condition to be transmitted, i.e. TX line is pulled low. Normal transmission can be recovered once this bit is cleared. Transmitter logic can be used as break timer. 1: If this bit is set, along with parityEn a fixed parity bit will be transmitted and expected. This fixed parity bit will be the complement of the bit 4. 0: Data byte along with parity bit will be sent and expected to be odd parity. 1: Data byte along with the parity bit will be even parity. Enable parity bit. 0: Data byte will be transmitted and received without parity bit. 1: Will enable the parity bit at the end of the data byte. This bit decides how many stop bits should be sent along with a data byte. 0: 1 stop bit transmitted 1: 2 stop bits transmitted if 6, 7 or 8 bit wordLenSel 1: 1.5 stop bits transmitted if 5 bit wordLenSel Receiver will always check for one stop bit. These bits will select the number of data bits to be transmitted and received. 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits
6
breakCntl
0
RW
5
stickParity
0
RW
4
evenParity
0
RW
3
parityEn
0
RW
2
stopBits
0
RW
1:0
wordLenSel
00
RW
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AS3524 C21 / C22 Data Sheet, Confidential Table 70 UART Line status register Name UART_LNSTATUS_REG Offset: 0x14 Bit 7 Bit Name FIFODataError Base AS3525_UART_BASE
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Default 0xC8110000
Line status register This register holds the status information of the data transfer. It gives information about the received data. Default 0 Access RU Bit Description 1: This bit is set when any data character in the FIFO has parity or framing error or break condition. 0: This bit is reset once the line status register (LINE_STATUS_REG) is read. This bit is reserved for future use. This bit is associated with the txDataEmpty interrupt. 1: Indicates that there is no data in txFIFO or the data register (UART_DATA_REG (Tx)). This bit is set once the data is shifted out. 0: This bit is reset once data is written into the data register (UART_DATA_REG (Tx)). This bit is associated with the rxLineStatus interrupt. 1: This bit is set if a break condition is detected, i.e. if a zero is detected on receive line for one full character duration. This condition will always cause framingError condition. This bit is associated with the rxLineStatus interrupt. 1: Indicates that the first stop bit of the received data byte is not valid, i.e. a zero is received in place of a one. This error condition causes the receiver to re-synchronize. This bit is associated with rxLineStatus interrupt. 1: Indicates that parity of the received data byte is different from the expected parity as set in the line control register (UART_LNCTL_REG). This bit is associated with the rxLineStatus interrupt. 1: Indicates an error condition which occurs when one character is fully assembled by the receiver but there is no space to write that byte. In FIFO mode, the content of the FIFO remains unaffected. If FIFO is disabled, the data register (UART_DATA_REG (Rx)) will be overwritten with the new data. 0: There is no data available. 1: There are one or more data bytes ready to be read by the processor.
6 5
Reserved txHoldRegEmpty
0 0
RU
4
breakDetect
0
RU
3
framingError
0
RU
2
parityError
0
RU
1
overrunError
0
RU
0
dataReady
0
RU
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AS3524 C21 / C22 Data Sheet, Confidential
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5.3.14 CGU - Clock generation unit
The clock generation unit generates all clocks for all modules on the chip. * * * * * * * * * Hardware programmable selection of clock input either from internal oscillator or external clock input Two on-chip PLL circuits for generation of internal clocks Programmable divider for generation of ARM922T clock (fclk) Programmable divider for generation of AMBA bus clock (pclk) Support of ARM922T fastbus, synchronous and asynchronous mode Included clock gating registersto optimise power consumption Three clock busses at input of all dividers (clk_main, clk_a, clk_b) for utmost flexibility Spike-free switches between divider clock inputs (clk_main, clk_a, clk_b) Independent clock dividers for peripheral modules
System startup
At startup, the system is configured in a way to run without the need of PLLs. PLLs are disabled and clk_main is used for generation of the clock for the ARM controller (fclk) and ARM AMBA bus (pclk). Within the clock gating register, only the clocks that are really necessary for initial boot are enabled: clock for ARM, for the internal 1-TRAM memory, for the internal ROM and for the external memory. So the boot loader can start either from internal ROM or from the external MPMC.
Clock switching
The system can be reconfigured to run from PLLA or PLLB. Because the 1-TRAM is a dynamic memory that must always get the clock for the internal memory refresh, this switching must be implemented in a way that the PCLK clock is never stopped. The easiest solution to fulfil this requirement is always switching back to clk_main for reconfiguring the PLLs. After reprogramming of the PLLs it must be checked that the PLLs are locked before the system is switched onto the PLL output frequency.
ARM922T and AMBA bus clock
The ARM processor can run in different modes. These modes can be set within the iA, nF bits of the ARM922T CP15 (coprocessor) register 1. Fastbus mode This is the default mode after startup. The ARM922T input clock frequency is the same as the AHB/APB bus frequency. Synchronous mode Within the synchronous mode, the ARM922T frequency must be higher than the AHB/APB bus frequency and it must be an integer multiple of the AHB/APB bus frequency. Advantage of the synchronous mode is a higher performance because of less synchronisation effort between the ARM922T and the AHB bus. Asynchronous mode Within asynchronous mode, the ARM922T frequency must be higher than the AHB bus frequency, but it can be completely asynchronous. Disatvantage is a slightly reduced performance of the system because of the higher effort for synchronisation between the ARM922T and AHB clock domains.
Block Diagram
The block diagram on the following page gives a detailed view of the structure of the CGU.
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AS3524 C21 / C22 Data Sheet, Confidential Figure 38 Clock generation unit block diagram
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AS3524 C21 / C22 Data Sheet, Confidential
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5.3.14.1 Input clock selection
Input clock is either coming directly from the clk_ext pin or from the internal 24MHz crystal oscillator. Usage of external pin or internal oscillator is selected by the dedicated pin clk_sel. Table 71 Clock Selection Clk_sel 0 1 Description clk_main = clk_int clk_main = clk_ext
Three main internal clocks are generated as source for all clock dividers for all modules. * * clk_a, clk_b: the outputs of two independently configurable PLLs. clk_main: this clock is always available without the need of configuring any internal PLL
An important constraint of the system is the memory type of the RAM: the internal 1-TRAM needs refresh cycles, with the following important restrictions: the free running AHB/APB clock (PCLK) for the 1-TRAM must always be present: also for changing frequency settings, this must be taken into account (e.g. switch from clk_main to PLL output only after PLL is settled (start-up time). * the minimum frequency for the free running AHB/APB clock of the 1-TRAM is 20 MHz. Important note: Switching between the different frequencies must be done in a pre-defined order using the CGU-driver software. *
5.3.14.2 Clock Gating
For all peripheral clock domains clock gating is possible. Clock gating can be enabled/disabled by the corresponding bits within the clock control register CGU_PERI. After start-up, only the modules, which are necessary for booting the device, are enabled. These enabled peripherals are * * * * 1-TRAM controller and 1-TRAM macros external memory interface MPMC internal ROM vectored IR controller (VIC)
5.3.14.3 Interrupt generation
An interrupt can be generated after the PLL is locked.
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AS3524 C21 / C22 Data Sheet, Confidential
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5.3.14.4 PLL description
* * * * * runs on single power supply at 1.2 V (special power PADs are used within the chip layout to guarantee lowest jitter: vddapll, vssapll which are connected to vdd_core, vss_core within the BGA substrate) fully integrated with internal loop filter VCO operating frequency from 200 - 400 MHz phase comparator input frequency from 2 - 8 MHz low power dissipation of typical 2.5 mW
Figure 39 PLL block diagram
Programming and calculation of the PLL output frequency The output frequency is controlled by three programmable dividers within the PLL. These dividers are: the input divider NR, the feedback divider NF and the output divider NO. The divider settings are programmed by bits within CGU_PLLA, CGU_PLLB registers. The table on the following page gives the detailed formulas for setting the PLL output frequency.
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AS3524 C21 / C22 Data Sheet, Confidential Table 72 Setting the PLL output frequency Input divider NR.
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NR = 16 * R4 + 8*R3 + 4*R2 + 2*R1 + R0
Feedback divider NF:
NF = 2 * (128*F7 + 64*F6 + 32*F5 + 16*F4 + 8*F3 + 4*F2 + 2*F1 + F0
Output divider NO: Output divider setting OD0=0, OD1=0 OD0=1, OD1=0 OD0=0, OD1=1 OD0=1, OD1=1 NO (output divider value) Not allowed 1 2 4
The PLL output frequency is calculated with following formula Output frequency
fout =
NF fin NR NO
Comparison frequency
fref = fvco =
fin NR NF fin NR
VCO frequency
Following constraints must be followed for the comparison and output frequency:
2 MHz fref 8 MHz 200 MHz fVCO 400 MHz
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AS3524 C21 / C22 Data Sheet, Confidential Clock Constraining
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Different clocks are constraint to different maximum clock speeds. As the clock frequencies can be set by software, care must be taken not to exceed these maximum clock frequencies. Table 739 Clock Constraining Clock Domain FCLK PCLK MPMC_CLK I2SI MCLK I2SO MCLK USB CLK IDE CLK MS CLK Max. Freq. [MHz] 250 65 90 65 30 48 90 40 Description Processor Clock AHB/APB bus clock MPMC (external memory interface) clock I2S input interface master clock I2S output interface master clock USB interface clock IDE interface clock Memory Stick Interface clock
Figure 40 Clock Generation Unit Block Diagram
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AS3524 C21 / C22 Data Sheet, Confidential
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5.3.14.5 Clock Generation Unit Registers
Table 20 CGU Registers Register Name CGU_PLLA CGU_PLLB CGU_PLLASUP CGU_PLLBSUP CGU_PROC CGU_PERI CGU_AUDIO CGU_USB CGU_INTCTRL CGU_IRQ CGU_COUNTA CGU_COUNTB CGU_IDE CGU_MS CGU_DBOP Base Address AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE AS3525_CGU_BASE Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 Note PLLA configuration register PLLB configuration register PLLA supervisor register PLLB supervisor register processor clock control register peripheral clock control register audio clock control register USB clock control register CGU interrupt mask and enable register interrupt clear and lock status register PLLA lock counter register PLLB lock counter register IDE clock control register Memory Stick clock control register DBOP clock controller register
Table 21 CGU_PLLA Register Name CGU_PLLA Offset0x00 Bit 14:13 12:8 7:0 Bit Name PLLA_OD [1:0] PLLA_R [4:0] PLLA_F [7:0] Base AS3525_CGU_BASE PLLA Configuration Register The CGU_PLLA register is used to configure the PLL A Default 0x00 0x00 0x00 Access R/W R/W R/W Bit Description PLLA output divider control, 2 bit PLLA input divider control, 5-bit PLLA feedback divider control, 8 bit Default 0x00
Table 22 CGU_PLLB Register Name CGU_PLLB Offset0x04 Bit 14:13 12:8 7:0 Bit Name PLLB_OD [1:0] PLLB_R [4:0] PLLB_F [7:0] Base AS3525_CGU_BASE PLLB Configuration Register The CGU_PLLB register is used to configure the PLL B Default 0x00 0x00 0x00 Access R/W R/W R/W Bit Description PLLB output divider control, 2 bit PLLB input divider control, 5-bit PLLB feedback divider control, 8 bit Default 0x00
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AS3524 C21 / C22 Data Sheet, Confidential Table 23 PLLA Supervisor Register Name CGU_PLLASUP Offset0x08 Bit 3 2 1 0 Bit Name PLLA_PD PLLA_OEB PLLA_BP PLLA_FIN_SEL Base AS3525_CGU_BASE
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Default 0x08
PLLA Supervisor Register This register contains control bits of the PLLA which are used very rarely, but have major impact on the functionality of the system. Default 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W Bit Description PLLA power down if SET PLLA output enable, active low PLLA bypass if SET PLLA clock source select 0: clk_int [PAD] 1: clk_ext [PAD]
Table 24 PLBB Supervisor Register Name CGU_PLLBSUP Offset0x0c Bit 3 2 1 0 Bit Name PLLB_PD PLLB_OEB PLLB_BP PLLB_FIN_SEL Base AS3525_CGU_BASE Default 0x08
PLLB Supervisor Register This register contains control bits of the PLLB which are used very rarely, but have major impact on the functionality of the system. Default 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W Bit Description PLLB power down if SET PLLB output enable, active low PLLB bypass if SET PLLB clock source select 0: clk_int [PAD] 1: clk_ext [PAD]
Table 25 Processor Clock Controller Register Name CGU_PROC Offset0x10 Bit 7:4 Bit Name FCLK_POSTDIV_SEL [3:0] Base AS3525_CGU_BASE Default 0x00
Processor Clock Controller Register This register contains control bits for ARM processor clock generation => FCLK. Default 0x00 Access R/W Bit Description post divider division ratio => post_div = 1/(fclk_postdiv_sel + 1) pre divider (fractional) division ratio 00: pre_div = 1/1 01: pre_div = 7/8 10: pre_div = 6/8 11: pre_div = 5/8 clkin select 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main)
3:2
FCLK_PREDIV_SEL [1:0]
0x00
R/W
1:0
FCLK_SEL[1:0]
0x00
R/W
NOTE: f(fclk) := f(clkin) * pred_div * post_div;
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AS3524 C21 / C22 Data Sheet, Confidential
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Table 26 Peripheral Clock Controller Register Name CGU_PERI Offset0x14 Bit 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Bit Name MBIST_EN EXTMEM_EN EXTMEMIF_EN 1TRAM_EN ROM_EN VIC_EN DMAC_EN USB_EN I2SO_APB_EN I2SI_APB_EN I2C_EN I2C_AUDIO_EN GPIO_EN SDMCI_EN NANDFLASH_EN UART_EN WDOCNT_EN WDOIF_EN SSP_EN TIMER1_EN TIMER2_EN TIMERIF_EN PCLK_DIV1_SEL 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Base AS3525_CGU_BASE This register allows setting the peripheral clocks. Default Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Description memory bist manager clock enable external memory clock enable external memory AHB IF clock enable 1TRAM controller AHB IF clock enable ROM AHB IF clock enable vectored interrupt controller AHB IF clock enable DMA controller AHB IF clock enable USB controller AHB IF clock enable I2Sout APB IF clock enable I2Sin APB IF clock enable I2C master/slave APB IF clock enable I2C audio APB IF clock enable general purpose IO APB IF clock enable secure digital/multimedia APB IF clock enable NAND flash/Smart Media APB IF clock enable UART APB IF clock enable watchdog counter clock enable watchdog timer module APB IF clock enable synchronous serial port APB IF clock enable timer module timer1 clock enable timer module timer2 clock enable timer module APB IF clock enable Default 0x0F800000
Peripheral clock controller register
division ratio div1 (AHB/APB clock) => div1 = 1/(pclk_div1_sel + 1) PCLK_DIV0_SEL division ratio div0 (ext. memory clock) => div0 = 5:2 0x0 R/W [3:0] 1/(pclk_div0_sel + 1) clkin select b'00: clk_main 1:0 PCLK_SEL[1:0] 0x0 R/W b'01: plla_fout b'10: pllb_fout b'11: fclk CAUTION: Clock gating takes effect immediately! Software must assure that all transactions to/from the module are finished before the clock is disabled. CAUTION: The peripheral clock must not exceed 65 MHz. The software must assure that requirement. Note: f(clk_extmem) := f(clkin) * div0; f(pclk) := f(clkin) * div0 * div1;
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AS3524 C21 / C22 Data Sheet, Confidential Table 27 Audio Clock Controller Register Name CGU_AUDIO Offset0x18 Bit 24 23 22:14 Bit Name I2SI_MCLK2PAD_EN I2SI_MCLK_EN I2SI_MCLK_DIV_SEL [8:0] Base AS3525_CGU_BASE
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Default 0x00
Audio Clock Controller Register This register allows setting the audio clock to I2S input and output interface. Default 0 0 0x0 Access R/W R/W R/W Bit Description I2S audio input clock (I2SI_MCLK) to PAD connection enable I2S audio input clock (I2SI_MCLK) enable
I2Sin audio IF clock 1/(i2si_mclk_div_sel + 1) division ratio => div_i =
13:12
ISI_MCLK_SEL[1:0]
0x0
R/W
I2SI_MCLK clkin select 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main) I2S audio output clock (I2SO_MCLK) enable
I2Sout audio IF clock 1/(i2so_mclk_div_sel + 1) division ratio => div_o =
11 10:2
I2SO_MCLK_EN I2SO_MCLK_DIV_SEL [8:0]
0 0x0
R/W R/W
1:0
ISO_MCLK_SEL[1:0]
0x0
R/W
I2SO_MCLK clkin select 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main)
Note: The clock gating bits in this register apply only to the audio clocks. To enable/disable the APB parts of the corresponding I2S IF CGU_PERI has to be configured. f(i2si_mclk) := f(I2SI_mclk clkin) * div_i; f(i2so_mclk) := f(I2SO_mclk clkin) * div_o;
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AS3524 C21 / C22 Data Sheet, Confidential Table 28 Processor USB Clock Controller Register Name CGU_USB Offset0x1c Bit 5 Bit Name USB_CLK_EN Default 0x00 Access R/W Base AS3525_CGU_BASE
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Default 0x00
USB Clock ControllerRegister This register allows setting the USB PHY interface clock. Bit Description USB PHY clock enable => clk_usb division ratio 0: div = 1/1 > 0: div = 1/(2*n); (even division factors only) clkin select 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main)
4:2
USB_DIV_SEL [2:0]
0x00
R/W
1:0
USB_SEL[1:0]
0x00
R/W
Note: The clock gating bit applies only to the USB PHY clock. To enable/disable the clock to the AHB part (USB CORE) CGU_PERI has to be configured. f(clk_usb) = f(clk_core_48m) = f(clkin) * div; Table 29 Interrupt Mask and PLL Lock Status Register Name CGU_INTCTRL Offset: 0x20 Bit 3 2 1 0 Bit Name INT_EN_PLLB_LOCK INT_EN_PLLA_LOCK PLLB_LOCK PLLA_LOCK Default 0x00 0x00 0x00 Base AS3525_CGU_BASE Default 0x00
Interrupt Mask and PLL Lock Status Register
Access R/W R/W R R
Bit Description interrupt on PLLB lock enable (R/W) interrupt on PLLA lock enable (R/W) PLLB lock status, locked if SET (not cleared on read) PLLA lock status, locked if SET (not cleared on read)
Table 30 Interrupt Clear Register Name CGU_IRQ Offset: 0x24 Bit 1 0 Bit Name PLLB_LOCK PLLA_LOCK Default 0x00 0x00 Access R R Base AS3525_CGU_BASE Interrupt Clear Register Default 0x00
Bit Description PLLB lock status, locked if SET (not cleared on read) PLLA lock status, locked if SET (not cleared on read)
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AS3524 C21 / C22 Data Sheet, Confidential Table 31 PLL A Lock Counter Register Name CGU_COUNTA Offset: 0x28 Bit 7:0 Bit Name COUNTA[7:0] Default 0x00 Access R/W Base AS3525_CGU_BASE
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Default 0x20
PLL A Lock Counter Register
Bit Description number of PLL A's fout-clock cycles until the LOCKA bit is set
Table 32 PLL B Lock Counter Register Name CGU_COUNTB Offset: 0x2c Bit 7:0 Bit Name COUNTB[7:0] Default 0x00 Access R/W Base AS3525_CGU_BASE PLL B Lock Counter Register Default 0x20
Bit Description number of PLL B's fout-clock cycles until the LOCKB bit is set
Table 33 IDE Clock Controller Register Name CGU_IDE Offset: 0x30 Bit 7 6 5:2 Bit Name IDEIF_CLK_EN IDE_CLK_EN IDE_DIV_SEL [2:0] 0 0 0x0 Base AS3525_CGU_BASE IDE Clock Controller Register This register allows setting the IDE interface clocks. Default Access R/W R/W R/W Bit Description IDE AHB IF clock enable IDE IF clock enable (90MHz domain) => clk_ide division ratio => div = 1/(ide_div_sel + 1) clkin select (clk_ide) 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main) Default 0x20
1:0
IDE_SEL[1:0]
0x0
R/W
Note: f(clk_ide) := f(clkin) * div;
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AS3524 C21 / C22 Data Sheet, Confidential Table 34 Memory Stick (MS) Clock Controller Register Name CGU_MS Offset: 0x34 Bit 8 7 6:2 Bit Name MSIF_CLK_EN MS_CLK_EN MS_DIV_SEL [2:0] 0 0 0x0 Base AS3525_CGU_BASE
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Default 0x00
MS Clock Controller Register This register allows setting the MS interface clocks. Default Access R/W R/W R/W Bit Description MS APB IF clock enable MS IF clock enable (20/40MHz domain) => clk_ms division ratio => div = 1/(ms_div_sel + 1) clkin select (clk_ms) 00: clk_main 01: plla_fout 10: pllb_fout 11: reserved (clk_main)
1:0
MS_SEL[1:0]
0x0
R/W
Note: f(clk_ms) = f(clkin) * div; Table 35 Data Block Output Port (DBOP) Clock Controller Register Name CGU_DBOP Offset: 0x38 Bit 3 2:0 Note: Bit Name DBOP_EN DBOP_PREDIV_SEL [2:0] 0 0x0 Base AS3525_CGU_BASE DBOP Clock Controller Register This register allows setting the DBOP interface clocks. Default Access R/W R/W Bit Description DBOP APB IF clock enable division ratio => div = 1/(dbop_prediv_sel + 1) Default 0x00
Setting DBOP_EN will enable both clocks (push/APB and pop) immediately. clk_dbop clock (pop clock) generation uses DBOP APB IF clock as input clock. f(clk_dbop) = f(PCLKDBOP) * div;
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AS3524 C21 / C22 Data Sheet, Confidential Figure 41 Table with verified CGU frequency settings for Audio and USB applications with 24MHz crystal
Fref nf nr no [MHz] fvco [MHz] plla_fout [MHz] fclk_ pre fclk_ post fclk [MHz] pclk_ div0 pclk_ div1 pclk [MHz] mclk_ div mclk [Hz] fsaudio [Hz]
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faudio error [%]
usb_ div
fusbphy [Hz]
fusb error [%]
fsaudio target [Hz]
CPU clock mode
Target: 48.000 Hz 48 24 41 23 6 3 8 5 1 3 2 3 4,000 8,000 3,000 4,800 384,000 384,000 246,000 220,800 384,000 96,000 123,000 55,200 0,00 0,00 0,00 0,00 5,00 1,00 1,00 0,00 64,000 48,000 61,500 55,200 0 0 0 0 0 0 0 0 64,000 48,000 61,500 55,200 61 15 19 8 6.193.548 6.000.000 6.150.000 6.133.333 48.387 46.875 48.047 47.917 0,806 -2,344 0,098 -0,174 3 1 48.000.000 48.000.000 0,000 0,000 48000 48000 48000 48000 Fastbus Fastbus fastbus fastbus
Target: 44.100 Hz 48 24 47 79 47 6 3 10 12 10 1 3 2 3 3 4,000 8,000 2,400 2,000 2,400 384,000 384,000 225,600 316,000 225,600 384,000 96,000 112,800 79,000 56,400 0 0 0 0 0 5 1 1 1 1 64,000 48,000 56,400 39,500 28,200 0 0 0 0 0 0 0 0 0 0 64,000 48,000 56,400 39,500 28,200 67 16 19 13 9 5.647.059 5.647.059 5.640.000 5.642.857 5.640.000 44.118 44.118 44.063 44.085 44.063 0,040 0,040 -0,085 -0,034 -0,085 3 1 48.000.000 48.000.000 0,000 0,000 44100 44100 44100 44100 44100 fastbus fastbus fastbus fastbus fastbus
Target: 32.000 Hz 48 24 41 31 6 3 6 7 1 3 3 3 4,000 8,000 4,000 3,429 384,000 384,000 328,000 212,571 384,000 96,000 82,000 53,143 0 0 0 0 5 1 1 1 64,000 48,000 41,000 26,571 0 0 0 0 0 0 0 0 64,000 48,000 41,000 26,571 93 22 19 12 4.085.106 4.173.913 4.100.000 4.087.912 31.915 32.609 32.031 31.937 -0,266 1,902 0,098 -0,197 3 1 48.000.000 48.000.000 0,000 0,000 32000 32000 32000 32000 fastbus fastbus fastbus fastbus
Target: 24.000 Hz 48 24 41 6 3 8 1 3 2 4,000 8,000 3,000 384,000 384,000 246,000 384,000 96,000 123,000 0 0 0 5 1 1 64,000 48,000 61,500 0 0 0 0 0 0 64,000 48,000 61,500 124 30 39 3.072.000 3.096.774 3.075.000 24.000 24.194 24.023 0,000 0,806 0,098 3 1 48.000.000 48.000.000 0,000 0,000 24000 24000 24000 fastbus fastbus fastbus
Target: 22.050 Hz 48 24 47 6 3 10 1 3 2 4,000 8,000 2,400 384,000 384,000 225,600 384,000 96,000 112,800 0 0 0 5 1 1 64,000 48,000 56,400 0 0 0 0 0 0 64,000 48,000 56,400 135 33 39 2.823.529 2.823.529 2.820.000 22.059 22.059 22.031 0,040 0,040 -0,085 3 1 48.000.000 48.000.000 0,000 0,000 22050 22050 22050 fastbus fastbus fastbus
Target: 16.000 Hz 48 24 41 6 3 6 1 3 3 4,000 8,000 4,000 384,000 384,000 328,000 384,000 96,000 82,000 0 0 0 5 1 1 64,000 48,000 41,000 0 0 0 0 0 0 64,000 48,000 41,000 187 46 39 2.042.553 2.042.553 2.050.000 15.957 15.957 16.016 -0,266 -0,266 0,098 3 1 48.000.000 48.000.000 0,000 0,000 16000 16000 16000 fastbus fastbus fastbus
Target: 12.000 Hz 48 24 41 6 3 6 1 3 3 4,000 8,000 4,000 384,000 384,000 328,000 384,000 96,000 82,000 0 0 0 5 1 1 64,000 48,000 41,000 0 0 0 0 0 0 64,000 48,000 41,000 249 62 52 1.536.000 1.523.810 1.547.170 12.000 11.905 12.087 0,000 -0,794 0,727 3 1 48.000.000 48.000.000 0,000 0,000 12000 12000 12000 fastbus fastbus fastbus
Target: 11.025 Hz 48 24 41 6 3 6 1 3 3 4,000 8,000 4,000 384,000 384,000 328,000 384,000 96,000 82,000 0 0 0 5 1 1 64,000 48,000 41,000 0 0 0 0 0 0 64,000 48,000 41,000 271 67 57 1.411.765 1.411.765 1.413.793 11.029 11.029 11.045 0,040 0,040 0,184 3 1 48.000.000 48.000.000 0,000 0,000 11025 11025 11025 fastbus fastbus fastbus
Target: 8.000 Hz
48 24 41
6 3 6
1 3 3
4,000 8,000 4,000
384,000 384,000 328,000
384,000 96,000 82,000
0 0 0
5 1 1
64,000 48,000 41,000
0 0 0
0 0 0
64,000 48,000 41,000
374 93 79
1.024.000 1.021.277 1.025.000
8.000 7.979 8.008
0,000 -0,266 0,098
3 1
48.000.000 48.000.000
0,000 0,000
8000 8000 8000
fastbus fastbus fastbus
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5.3.15 CCU - Chip Control Unit
Following chapters describe the functions of the CCU. Table 74 CCU Registers Register Name CCU_SRC CCU_SRL CCU_MEMMAP CCU_IO CCU_SCON CCU_VERS CCU_SPARE1 CCU_SPARE2 Base Address AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE AS3525_CCU_BASE Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C Note Software reset control register Software reset lock register Memory map register IO configuration register System configuration register Chip version register spare register 1 (for future use) spare register 2 (for future use)
5.3.15.1 Reset Controller
* Generation of the internal reset: the external reset pin XRES is used to generate the internal global reset. This internal reset is synchronised to clk_main and the active reset time is enlarged. This is necessary to wait for the startup of the DC/DC converter and LDO's that are generating the supplies of the digital chip. The time assumed for this startup is 10 ms, therefore 2^18 cycles of clk_main are counted before the internal reset is released. This mechanism is also used for the WATCHDOG reset. Softreset: for each module, the reset can also be generated by SW control. For this purpose, the SW can write to the software reset control register (CCU_SRC). To avoid unintended SW resets, the access to this control register is locked by the SW reset lock register (CCU_SRL). So the correct usage is: * * * write CCU_SRC write CCU_SRL (magic number 0x1A720212) to CCU_LOCK to activate resets write CCU_SRL (0x00000000) to deactivate resets
*
Table 75 Software Reset Control Register Name CCU_SRC Offset: 0x0000h Bit 24 23 22 21 20 19 18 17 Bit Name DBOP_EN MBIST_EN SPDIF_EN TIMER_EN SSP_EN WDO_EN IDE_EN IDE_AHB_EN Base AS3525_CCU_BASE Default 0x00
Software Reset Control Register Writing a logic 1 to the single bits in the read/write register enables resets to each module. Default 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit Description 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: enable DBOP reset disable DBOP reset enable MBIST manager reset disable MBIST manager reset enable SPDIF reset disable SPDIF reset enable timer module reset disable timer module reset enable synchronous serial port reset disable synchronous serial port reset enable watchdog timer module reset disable watchdog timer module reset enable compact flash/IDE reset (except AHB part) disable compact flash/IDE reset (except AHB part) enable compact flash/IDE's AHB interface reset disable compact flash/IDE's AHB interface reset
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AS3524 C21 / C22 Data Sheet, Confidential Name CCU_SRC Offset: 0x0000h Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name UART_EN NAF_EN SDMCI_EN GPIO_EN I2C_AUDIO_EN I2C_EN MMS_EN I2SI_APB_EN I2SO_APB_EN USB_AHB_EN USB_PHY_EN DMAC_EN VIC_EN RAMC_EN 1TRAM_EN MPMC_EN BRIDGE_EN Base AS3525_CCU_BASE
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Default 0x00
Software Reset Control Register Writing a logic 1 to the single bits in the read/write register enables resets to each module. Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: Bit Description enable UART interface reset disable UART interface reset enable NAND flash/Smart Media interface reset disable NAND flash/Smart Media interface reset enable secure digital/multimedia interface reset disable secure digital/multimedia interface reset enable general purpose IO reset disable general purpose IO reset enable audio I2C interface reset disable audio I2C interface reset enable master/slave I2C interface reset disable master/slave I2C interface reset enable memory stick interface reset disable memory stick interface reset enable I2S input interface reset for APB part disable I2S input interface reset for APB part enable I2S output interface reset for APB part disable I2S output interface reset for APB part enable USB AHB reset disable USB AHB reset enable USB PHY reset disable USB PHY reset enable DMA controller reset disable DMA controller reset enable vectored interrupt cell reset disable vectored interrupt cell reset enable RAMC reset disable RAMC reset enable 1TRAM reset disable 1TRAM reset enable external memory AHB reset disable external memory AHB reset enable bridge reset disable bridge reset
Table 76 Software Reset Lock Register Name CCU_SRL Base AS3525_CCU_BASE Default 0x00
Offset: 0x0004h
Software Reset Lock Register Use of this register enables the software reset selected with Software Reset Control Register. Writing a value of 0x1A720212 will enable the selected reset; writing any other value will not enable software reset. Default 0 Access R/W Bit Description 0x1A720212: enables selected reset Other values: no effect
Bit 0:31
Bit Name software_reset_lock
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5.3.15.2 IO_PADRING functions
Within the IO_PADRING module all multiplexing for selecting alternative functions is implemented. The selection of active functions is chosen within the IO_configuration_register. Following table gives a description of the IO configurations:
Table 77 IO_PADRING Configurations Name CCU_IO Offset: 0x000Ch Bit 8:7 Bit Name naf_ce_sel[1:0] Base AS3525_CCU_BASE Default 0x00
IO Configuration Registers With this read/write registers the functionality of IOs are controlled which provides several different functions Default 0 Access R/W Bit Description these bits select which output is used for NAF ce_n. 0: naf_ce0_n 1: naf_ce1_n 2: naf_ce2_n 3: naf_ce3_n test mode: 1: pll output clock is available at a GPIO Pin 1: the IDE input/output configuration is set SPI used in master mode: 1: pin SSP_FSSOUT always 0 0: pin SSP_FSSOUT generated by SSP hardware block SPI used in slave mode: spi_flash_mode hast to be switched to 0 00: XPD works as general purpose IO 01: SD-MCI interface 10: the XPD[5:0] are configured to support MS, XPD[7:6} are general IO pins 11: reserved (XPD works as general IO) 1: the I2C master/slave IO configuration is set 1: the uart IO configuration is set
6 5 4
pll_probe_en ide_sel spi_flash_mode
0 0 0
R/W R/W R/W
3:2
xpd_func_sel(1:0)
0
R/W
1 0
i2c_ms_sel uart_sel
0 0
R/W R/W
5.3.15.3 Other CCU functions
With the CCU_MEMMAP register, the remap(r/w) and int_boot_sel (read only) bits are accessible. Table 78 Memory Map Register Name CCU_MEMMAP Offset: 0x0008h Bit 1 Bit Name INT_BOOT_SEL Base AS3525_CCU_BASE Default N/A
Memory Map Register With the register the remap(r/w) and int_boot_sel (r only) bits are accessible. Default external pin XPC[0] 0 Access R Bit Description Boot selection 1: internal ROM 0: external memory interface Defines memory mapping 1: RAM 0: ROM
0
REMAP
R/W
If the INIT_BOOT_SEL is 0 (boot from external memory interface), following pins will be latched at startup to define the MPMC interface settings: * * mpmc_stcs1mw[0] mpmc_stcs1pol * * mpmc_stcs1pb mpmc_rel1config
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5.3.15.4 Additional Chip Control Unit Registers
Table 79 System Configuration Register Name CCU_SCON Offset: 0x0010h Bit 0 Bit Name priority_config Base AS3525_CCU_BASE System Configuration Register This read/write register controls system parameters. Default 0 Access R/W Bit Description AHB master's priority configuration: 0: Configuration A (default) Highest priority: TIC (Test Interface Controller) - for production test only 2 nd highest priority: ARM922T 3 rd highest priority: DMA 4 th highest priority: USB lowest priority: IDE 1: Configuration B Highest priority: TIC (Test Interface Controller) - for production test only 2 nd highest priority: DMA 3 rd highest priority: USB 4 th highest priority: IDE lowest priority: ARM922T Default 0x00
Table 80 Chip Version Register Name CCU_VERS Offset: 0x0014h Bit 31:12 11:0 Bit Name main_version_id(19 :0) sub_version_id(11: 0) Base AS3525_CCU_BASE Chip Version Register Version information can be read from this register. Default 0x2 0x1 Access R R Bit Description main version ID sub version ID Default 0x09
Table 81 Spare Register 1 Name CCU_SPARE1 Offset: 0x0018h Bit 31:9 8 7 6 5 4 3:2 1:0 Bit Name spare dma_sreq_SSPRX_off dma_sreq_SSPTX_off dma_sreq_DBOP_off dma_sreq_I2Sin_off dma_sreq_I2Sout_off spare mpmc_clk_inv Base AS3525_CCU_BASE Default 0x00
Metal ECO Spare Register This register implements 32bit spare FF's. Use for metal ECO redesign. Defau lt 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit Description spare bits to be used for metal ECO redesign if SET disableDMA single request of SSPRX module if SET disable DMA single request of SSPTX module if SET disable DMA single request of DBOP module if SET disable DMA single request of I2Sin module if SET disable DMA single request of I2Sout module if SET spare bits to be used for metal ECO redesign if SET spare bits used to invert output clocks mpmc_clk(1:0) if SET
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Table 82 Spare Register 2 Name CCU_SPARE2 Offset: 0x001Ch Bit 31:3 2:0 Bit Name spare bist_idle_cycle_ctrl Base AS3525_CCU_BASE Default 0x00
Metal ECO Spare Register This register implements 32bit spare FF's. Use for metal ECO redesign. Defau lt 0x00 0x00 Access R/W R/W Bit Description spare bits to be used for metal ECO redesign if SET internal RAM refresh cycle control bits of BIST_MGR module 000: idle every 32nd cycle (default) 100: idle every 16th cycle 110: idle every 8th cycle 111: idle every 4th cycle
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AS3524 C21 / C22 Data Sheet, Confidential
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6
6.1 6.2
Pinout and Packaging
Package Variants CTBGA180 Package Drawings
CTBGA (Thin ChipArray BGA) package technology is used for multi-chip-module (MCM) packaging.
6.2.1 Marking
Figure 42 CTBGA180 TOP View and Package Marking
Package Code AYYWWZZZ A
A ... for PB free
Y
Year
WW
working week assembly/packaging
ZZZ
Free choice
Figure 43 CTBGA224 Package Drawing Bottom/Side View
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6.2.2
1 A mpmc_ addr_0 dbop_ d13 dbop_ d12 vdd_peri _L
CTBGA180 Package Ball-out
2 mpmc_ addr_2 3 mpmc_ addr_4 4 mpmc_ addr_6 5 mpmc_ addr_10 6 mpmc_ addr_14 7 mpmc_ addr_18 8 vdd_me m 9 mpmc_ clk_0 10 mpmc_ clk_1 11 vdd_me m 12 mpmc_ data_2 13 mpmc_ data_4 14 mpmc_ data_6 15 mpmc_ data_8 16 mpmc_ data_10 17 mpmc_ data_12 18 mpmc_ data_14 dbop_ d14 mpmc_ addr_1 vss_peri _L mpmc_ addr_3 mpmc_ addr_5 mpmc_ addr_13 mpmc_ addr_17 mpmc_ dqm_0 mpmc_ dqm_1 mpmc_ bls_n_0 mpmc_ data_1 mpmc_ data_7 ssp_ fssout ssp_ clkout mpmc_ addr_11 mpmc_ addr_9 mpmc_ addr_7 mpmc_ mpmc_ dycs_n_0 dycs_n_1 mpmc_ mpmc_ stcs_n_0 stcs_n_1 mpmc_ addr_15 mpmc_ addr_19 mpmc_ ras_n mpmc_ bls_n_1 mpmc_ data_3 mpmc_ data_5 mpmc_ addr_8 mpmc_ addr_12 mpmc_ addr_16 mpmc_ mpmc_ vss_mem addr_20 fbclkin0 mpmc_ mpmc_ vss_mem cas_n data_0 mpmc_ data_9 mpmc_ data_11 mpmc_ data_13 mpmc_ data_15 vss_peri _R dbop_ d15 vdd_peri _R ide_ ha_0 ide_ ha_1 ide_ ha_2 vdd_ core
Figure 44 CTBGA180 Package Ball--out
B
C
D
E
xpc_7
xpc_4
ssp_rxd
F
xpc_6
xpc_3
xpc_1
ssp_txd
G
xpc_5
xpc_2
xpc_0
naf_d_7
ide_ reset_n vss_ core
H
vdd_ core
vss_ core i2si_sdat a_in i2si_sclk _out
xpa_0
naf_d_6
J
clk_ext
xpa_1
naf_d_3
naf_d_2
naf_d_5
naf_d_4
K
clk_int
xpa_2
xpa_3
naf_d_8
naf_d_9
naf_d_1
naf_d_0
L
usb_vdd a33t usb_vssa 33t
i2so_sclk
i2si_mclk
xpa_4
naf_d_12
naf_d_13
naf_d_10
naf_d_11
M
i2so_mcl k resetext_ n
i2si_sdat a i2so_sda ta
xpa_5
xpa_6
mpmc_ cke_0
mpmc_ naf_ce0_ naf_wp_ cke_1 n n
naf_cle
naf_d_14
naf_d_15
N
usb_dp
naf_ale
vss_peri _R
vdd_peri _R
P
usb_dm
id_dig
i2c_audi i2c_audi i2si_lrck_ out o_sda o_sck
xpa_7
mpmc_w mpmc_o naf_ce1_ naf_we_n e_n e_n n
xpd_0
xpd_1
xpd_2
xpd_3
R
usb_vssa 33t usb_vdd a33t usb_vdd a33c
usb_rext
xpd_4
xpd_5
T
vssapll
vss_core usb_xo _ana
intrq
i2so_lrck
jtag_trst_ naf_ce2_ jtag_tms jtag_tdo naf_re_n n n
xpb_0
xpb_1
xpb_2
vss_core _ana
xpd_6
U
xpd_7
V
VBUS
usb_vssa vdd_core vddapll 33c _ana
usb_xi
analog_t est
tmsel
clk_sel
jtag_tck
jtag_tdi
naf_ce3_ naf_bsy_ n n
xpb_3
xpb_4
xpb_5
vdd_core _ana
xpb_6
xpb_7
6.2.3 CTBGA180 Ball List
Table 83 CTBGA180 Ball List Ball Nr. BGA180 N3 K1 J1 V8 V7 Ball Name resetext_n clk_int clk_ext clk_sel tmsel PAD Type D IN ST D IN ST D IN ST PD D IN ST PD D IN ST PD I I/O I I I I Ball Description reset input (active low) clock input (10-26MHz) clock input (10-26MHz) clock select 0 (low): clock from clk_int is used for internal clk_main 1 (high): clock from pad clk_ext is used for internal clk_main test mode select
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AS3524 C21 / C22 Data Sheet, Confidential Ball Nr. BGA180 Ball Name PAD Type I/O
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Ball Description For testing purpose only, has to be set to "0".
P3
id_dig Port A
D IN ST (PU)
I
USB mini receptacle identifier Has to be connected to USB jack ID pin. GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port A GPIO IO, Port B static memory chip memory width setting for boot loader 0: 8 bit data bus 1: 16 bit data bus The value is latched at reset. DISPLAY control output GPIO IO, Port B static memory chip select polarity setting for boot loader 0: active LOW chip select 1: active high chip select The value is latched at reset. DISPLAY control output GPIO IO, Port B static memory byte lane polarity setting for boot loader 0: HIGH for reads, LOW for writes, used for we_n access 1: LOW for reads, LOW for writes, used for upper and lower byte access The value is latched at reset. DISPLAY control output GPIO IO, Port B test mode configuration (for testing purpose only !!!) The value is latched at reset. DISPLAY control output GPIO IO, Port B DISPLAY data input/output (high byte) GPIO IO, Port B DISPLAY data input/output (high byte) GPIO IO, Port B UART receive line DISPLAY data input/output (high byte) GPIO IO, Port B UART transmit line DISPLAY data input/output (high byte) GPIO IO, Port C
H5 J5 K5 K7 L7 M7 M8 P8
xpa[0] xpa[1] xpa[2] xpa[3] xpa[4] xpa[5] xpa[6] xpa[7] xpb[0]
D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR
IO IO IO IO IO IO IO IO IO I
Port B / DISPLAY / UART
T13
mpmc_stcs1mw[0 D IO ST PD LSR ]* dbop_c0 xpb[1] O IO I D IO ST PD LSR O IO I
T14
mpmc_stcs1pol* dbop_c1 xpb[2]
T15
mpmc_stcs1pb*
D IO ST PD LSR
dbop_c2 xpb[3] V13 mpmc_rel1config* D IO ST PD LSR dbop_c3 V14 V15 xpb[4] dbop_d[8] xpb[5] dbop_d[9] xpb[6] V17 uart_rxd dbop_d[10] xpb[7] V18 uart_txd dbop_d[11] Port C / DISPLAY / 2-WIRE SERIAL G5 xpc[0] D IO ST PD LSR D IO ST PU LSR D IO ST PU LSR D IO ST PD LSR D IO ST PD LSR
O IO I O IO IO IO IO IO I IO IO O IO IO
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AS3524 C21 / C22 Data Sheet, Confidential Ball Nr. BGA180 Ball Name PAD Type I/O I IntBootSel* dbop_d[0] xpc[1] F5 boot_sel[0] dbop_d[1] xpc[2] G3 boot_sel[1] dbop_d[2] xpc[3] F3 boot_sel[2] dbop_d[3] E3 G1 xpc[4] dbop_d[4] xpc[5] dbop_d[5] xpc[6] F1 cmd_ms_sck dbop_d[6] xpc[7] E1 cmd_ms_sda dbop_d[7] Port D / SD Card / Memory Stick xpd[0] P13 mci_dat[0] ms_sdio[0] xpd[1] P14 mci_dat[1] ms_sdio[1] xpd[2] P16 mci_dat[2] ms_sdio[2] xpd[3] P18 mci_dat[3] ms_sdio[3] xpd[4] R16 mci_cmd ms_sclk xpd[5] R18 mci_clk ms_bs xpd[6] T18 mci_fbclk ms_fbclk U18 xpd[7] mci_rod D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR IO IO IO IO IO IO IO IO IO IO IO IO IO O O IO O O IO I I IO O GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD data line MEMORY STICK data line GPIO IO, Port D MMC/SD command line MEMORY STICK clock line GPIO IO, Port D MMC/SD clock line MEMORY STICK bus state GPIO IO, Port D MMC/SD feedback clock MEMORY STICK feedback clock GPIO IO, Port D D IO ST PU LSR D IO ST PU LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR IO IO I IO IO I IO IO I IO IO IO IO IO IO IO IO IO IO IO
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Ball Description BOOT LOADER source select input 1: internal ROM 0: external ROM/Flash DISPLAY data input/output (low byte) GPIO IO, Port C BOOT LOADER type select input DISPLAY data input/output (low byte) GPIO IO, Port C BOOT LOADER type select input DISPLAY data input/output (low byte) GPIO IO, Port C BOOT LOADER type select input DISPLAY data input/output (low byte) GPIO IO, Port C DISPLAY data input/output (low byte) GPIO IO, Port C DISPLAY data input/output (low byte) GPIO IO, Port C 2-WIRE SERIAL master/slave clock line DISPLAY data input/output (low byte) GPIO IO, Port C 2-WIRE SERIAL master/slave data line DISPLAY data input/output (low byte)
MMC/SD resistor open drain control
2-wire serial Audio Master
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AS3524 C21 / C22 Data Sheet, Confidential Ball Nr. BGA180 P6 P5 Ball Name i2c_audio_sck i2c_audio_sda PAD Type D IO ST PU LSR D IO ST PU LSR I/O O O
austriamicrosystems
Ball Description 2-wire serial audio master clock line used for controlling the audio/PMU sub system 2-wire serial audio master data line used for controlling the audio/PMU sub system SSP master, frame or slave select SSP slave, frame select SSP master, clock line SSP slave, clock line SSP receive data input SSP transmit data output NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (low byte) IDE data line (low byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH data line (high byte) IDE data line (high byte) NAND FLASH command latch enable IDE DMA request used for DMA data transfers between host and device NAND FLASH address latch enable
Serial Synchronous Port E14 F14 E16 F16 ssp_fssout ssp_fssin ssp_clkout ssp_clkin ssp_rxd ssp_txd NandFlash / IDE K18 K16 J14 J12 J18 J16 H14 G14 K12 K14 L16 L18 L12 L14 M16 M18 M14 N14 naf_d[0] ide_hd[0] naf_d[1] ide_hd[1] naf_d[2] ide_hd[2] naf_d[3] ide_hd[3] naf_d[4] ide_hd[4] naf_d[5] ide_hd[5] naf_d[6] ide_hd[6] naf_d[7] ide_hd[7] naf_d[8] ide_hd[8] naf_d[9] ide_hd[9] naf_d[10] ide_hd[10] naf_d[11] ide_hd[11] naf_d[12] ide_hd[12] naf_d[13] ide_hd[13] naf_d[14] ide_hd[14] naf_d[15] ide_hd[15] naf_cle ide_dmarq naf_ale D IO ST LSR D IO ST LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O I O D IO ST PU LSR D IO ST PU LSR D IO ST PU LSR D IO ST PU LSR O I O I I O
(c) 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11
113 - 124
AS3524 C21 / C22 Data Sheet, Confidential Ball Nr. BGA180 Ball Name ide_iordy naf_wp_n M12 ide_intrq naf_ce0_n M11 ide_cs0_n D IO ST LSR D IO ST PD LSR PAD Type I/O I O I O O
austriamicrosystems
Ball Description IDE IO ready signal used by device to extend host data transfer cycles NAND FLASH write protect not IDE interrupt request used by device to interrupt the host controller NAND FLASH chip enable IDE chip select 0 used by the host to select command block registers in the device NAND FLASH chip enable IDE chip select 1 used by the host to select control block registers in the device NAND FLASH chip enable IDE host IO write strobe NAND FLASH chip enable IDE host IO read strobe NAND FLASH write enable not IDE DMA acknowledge used by the host to initiate DMA data transfers NAND FLASH read enable not IDE primary channel cable ID detect NAND FLASH ready / busy not IDE secondary channel cable ID select IDE host address IDE host address IDE host address IDE reset not, used by the host to reset the device IS2 data output, data output from digital core to audio sub system I2S serial clock, clock output from digital core to audio sub system I2S left/right clock, clock output from digital core to audio sub system I2S master clock, clock output from digital core to audio sub system I2S data input, data output from audio sub system to digital core I2S master serial clock serial clock output for external ADC if AS3525 is I2S master I2S slave serial clock serial clock input for external ADC if AS3525 is I2S slave I2S master, left/right clock left/right clock output for external ADC if AS3525 is I2S master I2S slave, left/right clock left/right clock input for external ADC if AS3525 is I2S master I2S master, master clock I2S data input data input from external audio ADC
114 - 124
naf_ce1_n P11 ide_cs1_n D IO ST LSR
O O
T11 V11 P12 T12 V12 E18 F18 G18 G16
naf_ce2_n ide_hiown naf_ce3_n ide_hiorn naf_we_n ide_dackn naf_re_n ide_npcblid naf_bsy_n ide_nscblid ide_ha[0] ide_ha[1] ide_ha[2] ide_reset_n I2S Output
D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D IO ST LSR D OUT LSR D OUT LSR D OUT LSR D OUT LSR
O O O O O O O I I I O O O O
N5 L3 T7 M3
i2so_sdata i2so_sclk i2so_lrck i2so_mclk I2S Input
D OUT LSR D OUT LSR D OUT LSR D OUT LSR
O O O O
M5
i2si_sdata i2si_sclk_out
D IN ST
I O
K3 i2si_sclk_in i2si_lrck_out P7 i2si_lrck_in L5 J3 i2si_mclk i2si_sdata_in
D IO ST LSR
I O
D IO ST LSR I D OUT LSR D IN ST PD O I
(c) 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11
AS3524 C21 / C22 Data Sheet, Confidential Ball Nr. BGA180 Ball Name spdif_data_in Audio Subsystem IRQ T6 T8 T9 V9 V10 T10 A1 C3 A2 E5 A3 E6 A4 J7 C4 H7 A5 G7 C5 E7 A6 G8 C6 E8 A7 G9 C7 M9 M10 A9 A10 C9 E9 E10 C10 J9 INTRQ jtag_trst_n jtag_tms jtag_tck jtag_tdi jtag_tdo mpmc_addr[0] mpmc_addr[1] mpmc_addr[2] mpmc_addr[3] mpmc_addr[4] mpmc_addr[5] mpmc_addr[6] mpmc_addr[7] mpmc_addr[8] mpmc_addr[9] mpmc_addr[10] mpmc_addr[11] mpmc_addr[12] mpmc_addr[13] mpmc_addr[14] mpmc_addr[15] mpmc_addr[16] mpmc_addr[17] mpmc_addr[18] mpmc_addr[19] mpmc_addr[20] mpmc_cke[0] mpmc_cke[1] mpmc_clk[0] mpmc_clk[1] mpmc_fbclkin mpmc_dqm[0] mpmc_dqm[1] mpmc_cas_n D IN ST D IN ST PD D IN ST PU D IN ST PU D IN ST PU D IO ST PU LSR D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D IO ST PD LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV I I I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I interrupt input JTAG reset not JTAG mode select JTAG clock JTAG data input JTAG data output EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line EXT. MEMORY address line JTAG Debugging IF PAD Type I/O I
austriamicrosystems
Ball Description SPDIF data input data input for SPDIF to I2S conversion
External Memory IF
mpmc_dycs_n[0] D OUT LSR LV
EXT. MEMORY clock enable0 used for SDRAM devices only EXT. MEMORY clock enable 1 used for SDRAM devices only EXT. MEMORY clock 0 used for SDRAM devices only EXT. MEMORY clock 1 used for SDRAM devices only EXT. MEMORY feedback clock used for SDRAM devices only EXT. MEMORY data mask 0 used for SDRAM devices and static memories EXT. MEMORY data mask 1 used for SDRAM devices and static memories EXT. MEMORY column address strobe not used for SDRAM devices only EXT. MEMORY dynamic memory chip select 0 not used for SDRAM devices only
(c) 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11
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AS3524 C21 / C22 Data Sheet, Confidential Ball Nr. BGA180 J10 G10 P9 K9 K10 E11 G11 P10 C12 E12 A12 G12 A13 H12 A14 E13 A15 C13 A16 C14 A17 C15 A18 C16 C1 B1 B18 C18 T1 L1 M1 R1 N1 P1 V5 Ball Name PAD Type I/O O O O O O O O O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO P P P P A A A
austriamicrosystems
Ball Description EXT. MEMORY dynamic memory chip select 1 not used for SDRAM devices only EXT. MEMORY row address strobe not used for SDRAM devices only EXT. MEMORY write enable not used for SDRAM devices and static memories EXT. MEMORY static memory chip select 0 not used for static memory devices only EXT. MEMORY static memory chip select 0 not used for static memory devices only EXT. MEMORY byte lane select 0 not used for static memory devices only EXT. MEMORY byte lane select 1 not used for static memory devices only EXT. MEMORY output enable not used for static memory devices only EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line EXT. MEMORY data line DISPLAY data input/output (high byte) DISPLAY data input/output (high byte) DISPLAY data input/output (high byte) DISPLAY data input/output (high byte) USB 3.3V analog power supply for OTG transceiver block USB 3.3V analog power supply for OTG transceiver block USB 3.3V analog ground supply for OTG transceiver block USB 3.3V analog ground supply for OTG transceiver block USB D+ signal from USB cable USB D- signal from USB cable USB crystal oscillator xi pin used for using external crystal for USB for testing purpose only, can be tied to USB crystal oscillator xo pin used for using external crystal for USB for testing purpose only, can be tied to USB external resistor connect clock generation ground or left floating clock generation ground or left floating
mpmc_dycs_n[1] D OUT LSR LV mpmc_ras_n mpmc_we_n mpmc_stcs_n[0] mpmc_stcs_n[1] mpmc_bls_n[0] mpmc_bls_n[1] mpmc_oe_n mpmc_data[0] mpmc_data[1] mpmc_data[2] mpmc_data[3] mpmc_data[4] mpmc_data[5] mpmc_data[6] mpmc_data[7] mpmc_data[8] mpmc_data[9] mpmc_data[10] mpmc_data[11] mpmc_data[12] mpmc_data[13] mpmc_data[14] mpmc_data[15] DBOP dbop_d[12] dbop_d[13] dbop_d[14] dbop_d[15] USB 2.0 OTG usb_vdda33t usb_vdda33t usb_vssa33t usb_vssa33t usb_dp usb_dm usb_xi PWP_VD_RDO_3V PWP_VD_RDO_3V PWP_VS_RDO_3V PWP_VS_RDO_3V USB_ESD_5VT USB_ESD_5VT ANA_BI_DNR_3V D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D IO ST PD LSR D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D OUT LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV D IO ST PD LSR LV
T5
usb_xo
ANA_BI_DNR_3V
A
R3
usb_rext
ANA_BI_RXT_3V
A
(c) 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11
116 - 124
AS3524 C21 / C22 Data Sheet, Confidential Ball Nr. BGA180 Ball Name PAD Type I/O
austriamicrosystems
Ball Description analog signal to the external resistor for setting the bias current of the USB 2.0 OTG PHY, voltage level is 1.1-1.3V USB 3.3V analog power supply for common block USB 3.3V analog ground supply for common block
U1 V2 V6 V1
vdda33c usb_vssa33c analog_test VBUS Supply Balls
PWP_VD_ANA_3V PWP_VS_RDO_3V ANA_BI_DNR_3V
P P A
USB analog test input/output for testing purpose only, has to be left open USB20_VBUS_5VT_O AIO USB VBUS analog input TG P P P P P P P P P P P P P P P P P P P P 3.3V peripheral power supply 3.3V peripheral power supply 3.3V peripheral power supply 3.3V/2.5V/1.8V external memory power supply 3.3V/2.5V/1.8V external memory power supply 3.3V peripheral ground supply 3.3V peripheral ground supply 3.3V peripheral ground supply 3.3V (2.5V) external memory ground supply 3.3V (2.5V) external memory ground supply 1.2V core power supply 1.2V core power supply 1.2V core power supply (analog blocks) 1.2V core power supply (analog blocks) 1.2V PLL power supply 1.2V core ground supply 1.2V core ground supply 1.2V core ground supply (analog blocks) 1.2V core ground supply (analog blocks) 1.2V PLL ground suppl
D1 D18 N18 A8 A11 D3 D16 N16 C8 C11 H1 H18 V4 V16 V3 H3 H16 T4 T16 T3
vdd_peri_l vdd_peri_r vdd_peri_r vdd_mem vdd_mem vss_peri_l vss_peri_r vss_peri_r vss_mem vss_mem vdd_core vdd_core vdd_core_ana vdd_core_ana vddapll vss_core vss_core vss_core_ana vss_core_ana vssapll
P P P P P P P P P P P P P P P P P P P P
(c) 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11
117 - 124
AS3524 C21 / C22 Data Sheet, Confidential
austriamicrosystems
6.3
Pad Cell Description
6.3.1 Digital Pads
6.3.1.1 D IN ST 6.3.1.2 D IN PD ST
Figure 45 Digital Input with Schmitt Trigger
Figure 46 Digital Input with Schmitt Trigger and Pull-Down
Schmitt
Schmitt
PAD
C
PAD
C
6.3.1.3
D IN PU ST
6.3.1.4
D IN (PU)
Figure 47 Digital Input with Schmitt Trigger and Pull-Up
Figure 48 Digital Input with enable controlled Pull-Up
Schmitt
PAD
C
REN
PAD
C
6.3.1.5
D OUT LSR
6.3.1.6
D IO ST LSR
Figure 49 Digital Output with Limited Slew Rate
Figure 50 Digital Schmitt Trigger Input and Limited Slew Rate Output
I
PAD
Schmitt
C
I
PAD
(c) 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11
118 - 124
AS3524 C21 / C22 Data Sheet, Confidential
austriamicrosystems
6.3.1.7
D IO ST PU LSR
6.3.1.8
D IO ST PD LSR
Figure 51 Digital Schmitt Trigger Input with Pull-Up and Limited Slew Rate Output
Figure 52 Digital Schmitt Trigger Input with Pull-Down and Limited Slew Rate Output
Schmitt
Schmitt
C
C I PAD
I PAD
6.3.1.9
D OUT LSR LV
6.3.1.10 D IO ST PD LSR LV
Figure 54 Digital Schmitt Trigger Input with Pull-Down and Limited Slew Rate Output (low voltage)
Figure 53 Digital Output with Limited Slew Rate (low voltage)
I
PAD
Schmitt
C
I
PAD
7
7.1
Appendix
Memory MAP
ARM922T provides 32-bit address to access the peripherals and memory. With this 32-bit address ARM922T can access up to 4 Giga Bytes of memory. Cocoa does not use the complete 4 GB address space. Address 0x0000_0000 is mapped to internal ROM or External Memory interface based on the boot ROM selection by the external input pin (Port C, xpc[0] = intBootSel) Pin intBootSel=1 at startup selects the internal ROM, intBootSel = 0 selects the external memory. The address range starting at 0x0000_0000 is also mapped to internal RAM upon setting of the remap bit. This remap allows the user to select either RAM or ROM at 0x0000_0000. Table 84 Address Map S.No . Start (Base) Address 0x0000_0000 0x0000_0000 End Address Actual Block Size 128 KByte 4 MB Peripheral AHB Blocks 0x0001_FFFF 0x003F_FFFF Internal ROM External Memory IF (MPMC Bank1 - Ext Flash or Ext ROM) Embedded 1T-RAM Reserved External Memory IF Remap = 0 and IntBootSel = 1 Remap = 0 and IntBootSel = 0 Remap = 1 Aliased Comment
0x0000_0000 0x0100_0000 0x1000_0000
0x0004_FFFF 0x0FFF_FFFF 0x103F_FFFF
320 KByte 4 MB
(c) 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11
119 - 124
AS3524 C21 / C22 Data Sheet, Confidential S.No . Start (Base) Address End Address Actual Block Size
austriamicrosystems
Peripheral (MPMC Bank1 - Ext Flash or Ext ROM) Reserved External Memory IF (MPMC Bank2 - External LCD Controller) Reserved External Memory IF (MPMC Bank 4 - SDRAM) External Memory If (MPMC Bank5 - SDRAM) Reserved Internal ROM Reserved Embedded 1T-RAM Reserved Internal ROM Reserved Embedded 1T-RAM Reserved USB2.0 Slave VIC DMAC Slave ExtMemIFSlave MemoryStick Slave CompactFlash/IDE Slave ARM922T Slave Reserved APB blocks Nand Flash / Smart Media Interface BistManager SD-MCI Reserved Timer Watchdog Timer I2C Master/Slave I2C Audio Master SSP I2S IN Interface I2S OUT Interface GPIO A GPIO B GPIO C GPIO D Clock Generation Unit Chip Control Unit Debug UART DBOP reserved
Comment
0x1100_0000 0x2000_0000
0x1FFF_FFFF 0x203F_FFFF
4 MB
0x2100_0000 0x3000_0000
0x2FFF_FFFF 0x3FFF_FFFF
256 MB
0x4000_0000
0x4FFF_FFFF
256 MB
0x5000_0000 0x8000_0000 0x8002_0000 0x8100_0000 0x8105_0000 0xC000_0000 0xC002_0000 0xC100_0000 0xC105_0000 0xC600_0000 0xC601_0000 0xC602_0000 0xC603_0000 0xC604_0000 0xC605_0000 0xC606_0000 0xC607_0000 0xC800_0000 0xC801_0000 0xC802_0000 0xC803_0000 0xC804_0000 0xC805_0000 0xC806_0000 0xC807_0000 0xC808_0000 0xC809_0000 0xC80A_0000 0xC80B_0000 0xC80C_0000 0xC80D_0000 0xC80E_0000 0xC80F_0000 0xC810_0000 0xC811_0000 0xC812_0000 0xC813_0000
0x7FFF_FFFF 0x8001_FFFF 0x80FF_FFFF 0x8104_FFFF 0xBFFF_FFFF 0xC001_FFFF 0xC0FF_FFFF 0xC104_FFFF 0xC5FF_FFFF 0xC600_FFFF 0xC601_FFFF 0xC602_FFFF 0xC603_FFFF 0xC604_FFFF 0xC605_FFFF 0xC606_FFFF 0xC7FF_FFFF 0xC800_FFFF 0xC801_FFFF 0xC802_FFFF 0xC803_FFFF 0xC804_FFFF 0xC805_FFFF 0xC806_FFFF 0xC807_FFFF 0xC808_FFFF 0xC809_FFFF 0xC80A_FFFF 0xC80B_FFFF 0xC80C_FFFF 0xC80D_FFFF 0xC80E_FFFF 0xC80F_FFFF 0xC810_FFFF 0xC811_FFFF 0xC812_FFFF 0xC813_FFFF
128 KByte 320 KByte 128 KByte 320 KByte Few Few Few Few Few Few 4 KByte
Aliased Aliased Aliased Aliased
Few Few Few Few Few Few Few Few Few Few Few Few Few Few Few Few Few Few
(c) 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11
120 - 124
AS3524 C21 / C22 Data Sheet, Confidential
austriamicrosystems
7.2
Register definitions
This section gives a short overview of all module registers.
7.2.1 Base Address definitions
Each module register block starts at a specific base address. Table 85 Base Addresses REGISTER Name AS3525_RAM_BASE AS3525_USB_BASE AS3525_VIC_BASE AS3525_DMAC_BASE AS3525_EXTMEM_ITF_BASE AS3525_MEMSTICK_BASE AS3525_CF_IDE_BASE AS3525_NAND_FLASH_BASE AS3525_BIST_MANAGER_BASE AS3525_SD_MCI_BASE AS3525_TIMER_BASE AS3525_WDT_BASE AS3525_I2C_MS_BASE AS3525_I2C_AUDIO_BASE AS3525_SSP_BASE AS3525_I2SIN_BASE AS3525_I2SOUT_BASE AS3525_GPIO1_BASE AS3525_GPIO2_BASE AS3525_GPIO3_BASE AS3525_GPIO4_BASE AS3525_CGU_BASE AS3525_CCU_BASE AS3525_UART_BASE AS3525_DBOP_BASE Register Address 0x00000000 0xC6000000 0xC6010000 0xC6020000 0xC6030000 0xC6040000 0xC6050000 0xC8000000 0xC8010000 0xC8020000 0xC8040000 0xC8050000 0xC8060000 0xC8070000 0xC8080000 0xC8090000 0xC80A0000 0xC80B0000 0xC80C0000 0xC80D0000 0xC80E0000 0xC80F0000 0xC8100000 0xC8110000 0xC8120000
(c) 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11
121 - 124
AS3524 C21 / C22 Data Sheet, Confidential
austriamicrosystems
8 Ordering Information
Table 86 ordering information Device ID AS3524P[-Z] V D Number AS3524A-Z AS3524A-Z AS3524A-Z AS3524A-Z C21 C21 C22 C22 TRA T&R TRA T&A Package Type CTBGA 180 Delivery Form Tray Tape and Reel Tray Tape and Reel Description Pb-free
Where V = Version C21: C22: see chapter P = Package Type: A: CTBGA 180, Thin ChipArray Ball Grid Array, 10x10mm package size, 0.5mm ball pitch D = Delivery Form: TRA = Tray T&R = Tape and Reel Z = Pb-free Status: Z = Pb-free/ RoHS package type Version with initial Bootloader Version 1 Version with ROM mask update and changed Bootloader Version 2
(c) 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11
122 - 124
AS3524 C21 / C22 Data Sheet, Confidential
austriamicrosystems
9
Copyright
Copyright (c) 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks of their respective companies.
10
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical lifesupport or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
11
Contact Information
austriamicrosystems AG Business Unit Communications A 8141 Schloss Premstatten, Austria T. +43 (0) 3136 500 0 F. +43 (0) 3136 5692 info@austriamicrosystems.com
For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com
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123 - 124
AS3524 C21 / C22 Data Sheet, Confidential
austriamicrosystems
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